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Pre-anneal of cosi, to prevent formation of amorphous layer between ti-o-n and cosi

Inactive Publication Date: 2005-03-31
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Benefits of technology

[0015] annealing the Group IVA metal layer, the nitrogen passivation layer, and the Co or Ni silicide, wherein the nitrogen passivation layer substantially restricts the diffusion of metals from said Group IVA metal layer.
[0020] annealing the Group IVA metal layer in a nitrogen-containing ambient to form a Group IVA metal nitride diffusion barrier and an amorphous metal silicide, having a thickness of about 3.0 nm or less, between the metal nitride diffusion layer and the silicide, wherein the nitrogen passivation layer substantially restricts diffusion of the metal elements from the Group IVA metal layer; and

Problems solved by technology

Forming devices having a titanium oxynitride diffusion barrier atop a cobalt silicide has presented difficulty when processed with corresponding tungsten vias.
If the titanium nitride diffusion barrier layer is to thin to be an effective barrier to fluorine, the fluorine may attack the underlying amorphous titanium cobalt silicide layer resulting in a ruptured via producing an electrically open circuit.

Method used

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  • Pre-anneal of cosi, to prevent formation of amorphous layer between ti-o-n and cosi
  • Pre-anneal of cosi, to prevent formation of amorphous layer between ti-o-n and cosi
  • Pre-anneal of cosi, to prevent formation of amorphous layer between ti-o-n and cosi

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Embodiment Construction

[0033] The inventive method for forming a low resistance via will now be discussed in greater detail referring to the drawings accompanying the present invention. It is noted in the accompanying drawings like and corresponding elements are referred to by like reference numbers.

[0034] Referring to FIG. 2, a substrate 10 of silicon-containing material is first provided. Silicon-containing materials include, but are not limited to: silicon, single crystal silicon, polycrystalline silicon, silicon germanium, silicon-on-silicon germanium, amorphous silicon, silicon-on-insulator (SOI), silicon germanium-on-insulator (SGOI), and annealed polysilicon. The substrate may further comprise the source / drain regions 11 and gate region 12 of a complementary metal oxide semiconducting device. The gate region 12 may include a gate dielectric 9 and polysilicon gate conductor 13.

[0035] Referring to FIG. 3, a silicide region 15 is then formed atop the source and drain regions 11. A gate silicide regi...

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Abstract

The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.

Description

FIELD OF INVENTION [0001] The present invention relates to semiconductor devices and a method of manufacture, more particularly to an improved via interconnect to a silicide region. BACKGROUND OF THE INVENTION [0002] Barrier layers and silicide layers are often an integral part of semiconducting devices. Materials which function as barriers to metal diffusion may be incorporated in metal interconnect structures that are part of integrated circuits (ICs). Barriers to metal diffusion are typically required to generate reliable devices, since low-k interlayer dielectrics typically do not prohibit metal diffusion. [0003] Silicide contacts are of specific importance to IC's, including complementary metal oxide semiconductor (CMOS) devices because of the need to reduce the electrical resistance of the many Si contacts, at the source / drain and gate regions, in order to increase chip performance. Silicides are metal-silicon compounds that are thermally stable and provide for low electrical ...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L21/44H01L21/768H01L23/52
CPCH01L21/28518H01L21/76814H01L29/665H01L21/76855H01L21/76856H01L21/76843H01L23/485
Inventor BRULEY, JOHNCABRAL, CYRIL JR.LAVOIE, CHRISTIANWAGNER, TINA J.WANG, YUN YUWLLDMAN, HORATL S.HON, WONG KWONG
Owner GLOBALFOUNDRIES INC
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