Input/output buffer

Abstract

An input / output buffer. An input / output circuit has a transmission terminal coupled to an I / O pad, and a floating N-well region. A P-gate control circuit conveys the second gate control signal to the gate of the first PMOS transistor. A feedback detection device is coupled between the transmission terminal and an N-well control circuit to output a feedback signal according to an input voltage at the I / O pad. The N-well control circuit adjusts the voltage level at the N-well region of the first PMOS transistor according to the feedback signal output from the feedback detection device.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to an input / output buffer, and more particularly, to an input / output buffer capable of accepting an input logic signal voltage higher than the system voltage. [0003] 2. Description of the Related Art [0004] Conventionally, most IC devices are driven by a system voltage in the range of 0-5V. In these IC devices, high-voltage logic signals are set at the system voltage and low-voltage logic signals at the ground voltage. With advances in semiconductor technology, however, the system voltage can be reduced to 3.3V because the gate oxide layers in the IC device are thinner. Still lower system voltage may be possible in the future. In practice, however, an New 3.3V IC device is usually used in conjunction with older 5V peripheral devices. For instance, an New 3.3V VGA (video graphic adapter) may be used in conjunction with other older 5V peripheral devices in a personal computer. Compatibili...

AI Technical Summary

Benefits of technology

[0008] It is therefore an object of the present invention to prevent I / O buffer from undesired current leakage when accepting an input logic signal voltage higher than the system voltage.

[0009] According to the above mentioned object, the present invention provides an I / O buffer capable of preventing undesired current leakage without external control signals from core circuits.

[0011] When the I / O buffer operates in input mode, if the input signal to the transmission terminal is 5V higher than the system voltage of 3.3V, the feedback detection device outputs a feedback signal of 0V to N-well control circuit. The N-well control circuit 130 adjusts the voltage level at the floating N-well region of the first PMOS transistor 5V. When the voltage state at the transmission terminal is switched from 5V to 0V, lower than the system voltage of 3.3V, the feedback detection device outputs a feedback signal of 5V to N-well control circuit. The N-well control circuit adjusts the voltage level at the floating N-well region of the first PMOS transistor to the system voltage (3.3 V). Thus, undesired current leakage is prevented.

Problems solved by technology

Compatibility between the new 3.3V devices and the older 5V devices can thus be a problem.

However, this I / O buffer needs two external control signals TN and / TN from the core circuits (not shown) to control the voltage at the floating N-well region being above 3.3V, increasing circuit complexity and requiring more wafer area.

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