Formation of low resistance via contacts in interconnect structures

Abstract

A method of fabricating an interconnect structure including the steps of: forming a porous or dense low k dielectric layer on a substrate; forming single or dual damascene etched openings in the low k dielectric; placing the substrate in a process chamber on a cold chuck at a temperature about −200° C. to about 25° C.; adding to the process chamber a condensable cleaning agent (CCA) to condense a layer of CCA within the etched openings on the substrate; and activating at a temperature about −200° C. to about 25° C. Also provided is an interconnect structure having a substrate, a conductive material disposed on the substrate, a porous or dense low k dielectric layer disposed on the conductive material, wherein the low k dielectric layer has a single or dual damascene etched openings that expose a surface of the conductive material, and metallic lines and vias etched onto the low k dielectric layer; wherein the exposed conductive material has been treated with a CCA and activated in the cold to remove oxide, oxygen and carbon containing residues from the surface of the conductive material.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention generally relates to integrated circuits (ICs). More particularly, the present invention relates to interconnect structures, including multilevel interconnect structures fabricated by damascene methods in which the via contact resistance must be low. The present invention describes various methods and tooling for making improved interconnect structures based on copper damascene wiring having a reduced via contact resistance and stable resistance both during IC operation and reliability stress of the IC device. [0003] 2. Description of the Prior Art [0004] Generally, semiconductor devices include a plurality of circuits, which form an integrated circuit fabricated on a silicon single crystal substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires...

AI Technical Summary

Benefits of technology

[0010] It is therefore an object of the present invention to provide methods of improved fabrication of BEOL interconnect structures of the dual or single damascene type, with low via contact resistance.

[0011] It is also an object of the present invention to provide methods of improved fabrication of BEOL interconnect structures of the dual or single damascene type, in which all the vias on the IC are very stable in resistance (the via resistance does not change or goes down) after thermal cycling of the structure.

[0012] It is a further object of the present invention to provide methods for improved fabrication of BEOL interconnect structures of the dual or single damascene type in which all the vias on the IC have improved adhesion.

[0013] It is a further object of the present invention to provide methods for improved fabrication of BEOL interconnect structures of the dual or single damascene type in which the shapes of the etched via and trench openings are not distorted or changed during via cleaning.

[0014] It is a further object of the present invention to provide methods for improved fabrication of BEOL interconnect structures of the dual or single damascene type in which the bottoms of the etched trench openings are smooth after via cleaning and the other surfaces of the vias and lines remain smooth.

[0031] The via contacts prepared by the methods of the present invention are very stable during thermal cycles and during operation of the semiconductor device. Further, the via contacts prepared by the methods described herein have a lower resistance than the vias described in the prior art. In addition, in the present invention, the vias are surrounded by a liner (for example, see element 6 in FIG. 1) and the adhesion of the liner is stronger than it is in the vias described in the prior art. As a result, the interconnect structures of the present invention are more reliable and more stable than the interconnect structures of the prior art, because stronger liner adhesion leads to more reliable and stable interconnect structures.

Problems solved by technology

However, fabrication problems are associated with these prior art structures.

Another problem associated with these prior art structures is poor adhesion at the via contact, which leads to increased via resistance after the structure is cycled in temperature or after long periods of field operation.

The extreme case of increased via resistance is an open via with no contact to the line below, a fatal IC failure mode.

Poor adhesion is also due to the same contamination described above.

A further problem during interconnect fabrication is that the shapes and dimensions of the etched via and trench openings are correct after etch, but the shapes and dimensions are distorted, enlarged, degraded or roughened during via cleaning.

This problem is most acute when low modulus ultralow k (ULK) dielectrics (k<about 2.7) are used and the via cleaning includes Ar+ bombardment.

The Ar+ ions enlarge the via dimensions and erode the bottom of the trenches and even cause roughening of the trench bottom.

Pores in the ULK dielectric make this problem severe.

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