Spectral shaping dynamic encoder for a dac

Abstract

A tree-structured dynamic encoder generates an N-bit encoder output word in response to each encoder input word of a sequence of encoder input words, such that the number of encoder output word bits of value 1 equals a value of the encoder input word and such that positions bits of value 1 within the N-bit encoder output word for each give value of encoder word varies with time. Some or all of the switching blocks produce more than two block output words in response to each block input word. The dynamic encoder includes a tree of switching blocks, each dynamically encoding a block input word into more than one block output words, each having fewer bits than the block input word. A sum of values of the output words of each switching block always equals a value of that block's input word. A switching block of the highest layer of the tree receives each successive encoder input word as its block input word, and each switching block of each layer of the tree other than a lowest layer supplies each of its at least two block output words as a block input word to a separate switching block of a next lower layer of the tree. Each switching block of the lowest layer of the tree generates single-bit block output words, each forming a separate bit of the N-bit encoder output word.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates in general to multiple-bit digital-to-analog encoders (DACS) and in particular, to a spectral shaping dynamic encoder for a DAC. 2. Description of Related Art Delta-Sigma ADC Architecture FIG. 1 depicts a prior art delta-sigma analog-to-digital converter (ADC) 10 including a sample and hold (S / H) circuit 12, a delta-sigma modulator 14, and a digital decimator 16, for digitizing an analog input signal AIN to produce an output data sequence D representing the analog input signal. S / H circuit 12 samples the AIN signal on each pulse of a clock signal (CLOCK) at a rate much higher than the AIN signal bandwidth to produce a sequence of discrete analog samples a[n] supplied as input to delta-sigma modulator 14. Delta-sigma modulator 14 responds to each pulse of the CLOCK signal by generating an element of an M-bit wide output sequence x[n]. When each element of the x[n] sequence is, for example, M=1 bit...

AI Technical Summary

Benefits of technology

In accordance with the invention, at least one of the switching blocks produces more than two output words. For example, when N is a power of four, each switching block is suitably a “radix-4” switching block produces four output words in response to each input word. Such an encoder requires only log4(N) layers of switching blocks. When N is a power of two, but not a power of four, the top level switching block may be a “radix-2” switching block generating two output words while all other switching blocks may be radix-4 switching blocks. Such an encoder would require a total of 1+log4(N / 1) switching block layers. Prior art dynamic encoders employing only radix-2 switching blocks require log2(N) switching block layers. By reducing the number of switching block levels required, the invention increases a dynamic encoder's maximum allowable operating frequency.

Problems solved by technology

However, the feedback loop may not correct errors arising from any non-linearity of DAC 24.

Single-bit (M=1) delta-sigma data converters are popular because their 1-bit internal DACs are inherently linear, but a 1-bit data converter can achieve only relatively limited resolution for a given over-sampling ratio p. Sigma-delta modulator employing 1-bit DACs are also sensitive to timing errors such as sampling clock jitter and to other sources of error.

The nonlinearity of a multiple-bit DAC arises from mismatches in its internal components, and while a “mismatch-shaping” DAC exhibits nonlinear behavior, it shapes the error component frequencies of its output signal resulting from component mismatches so that they reside outside a frequency band of interest.

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