Power MOS transistor having capability for setting substrate potential independently of source potential

Abstract

A power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.

Description

[0001] 1. Field of the Invention[0002] The present invention relates to a power MOS transistor capable of passing a high level of drain current, which is formed of an array of MOSFET (metal-oxide-semiconductor field effect transistor) cells.[0003] 2. Description of the Prior Art[0004] Types of LDMOS FET (lateral diffusion MOSFET, referred to in the following as a LDMOS transistor), formed of an array of interconnected MOSFET cells to constitute a power MOS transistor, are known in the prior art. Such a transistor has a multi-layer configuration of connecting leads, to thereby enable the area occupied by the connecting leads to be reduced and to enable the wiring resistance within the transistor to be lowered. An example of such a prior art LDMOS transistor configuration is shown in FIGS. 20 and 21. As illustrated in the plan view of FIG. 20, this has a conventional stripe configuration of MOSFET cells (source cells and drain cells). The respective source electrodes of the source cel...

AI Technical Summary

Problems solved by technology

However in that case, it is necessary for the substrate contact area within each source cell to be large in size, so that the area occupied by each source cell becomes large, and hence the overall chip area that is occupied by the LDMOS transistor becomes large.

This is an especially serious problem when a power MOS transistor is to be utilized in a form of operation such as PWM (pulse width modulation), in which the transistor is repetitively switched between the ON and OFF states, and so repetitively changes between the transition condition and the fully ON condition, and such limiting to prevent excessive current flow through the power MOS transistor is to be applied, for example as described in Japanese patent No.

Due to the large number of drain electrodes and source electrodes which constitute a power MOS transistor, the total area of the gate electrodes is large, so that there is a significant amount of stray capacitance between the gate electrodes and the substrate.

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