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Method for controlling planeness during chemically mechanical polishing for ULSI multiple-layered copper wiring

A technology of chemical mechanics and control methods, which is applied in the direction of surface polishing machine tools, grinding/polishing equipment, polishing compositions containing abrasives, etc., can solve problems such as poor flatness and edge collapse, and achieve high flatness and reduce The problem of edge collapse, the effect of good dispersion

Inactive Publication Date: 2006-11-15
天津河北工业大学资产经营有限责任公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to overcome the above disadvantages, in order to solve the problem of poor flatness, especially serious edge slump, in the chemical mechanical polishing process of existing copper wiring, and to provide a high-concentration abrasive particle under alkaline conditions, chemical action Strong, strong complexation, no scratches, and low cost method for controlling flatness in chemical mechanical polishing of ULSI multilayer copper wiring

Method used

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  • Method for controlling planeness during chemically mechanical polishing for ULSI multiple-layered copper wiring

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Effect test

Embodiment 1

[0029] Preparation of polishing liquid: choose 25L silica sol with a particle size of 15nm as the abrasive, the concentration is 20%, and the ratio with deionized water is 1:1; choose FA / O chelating agent to adjust the pH value to 10; choose FA / OI type The active agent is used as a surfactant, the content is 10ml / l; select H 2 o 2 It is an oxidant with an oxidant content of 10ml / l. The polishing process conditions are: flow rate 1L / min, temperature 20°C, speed 60rpm / min, pressure 100g / cm 2 .

[0030] The polishing machine used in the experiment is C6382 type, and the polishing cloth is the fine throwing cloth of Taiwan Weiying Company.

Embodiment 2

[0032] Preparation of polishing solution: choose 35L silica sol with a particle size of 20nm as abrasive, the concentration is 50%, and the ratio of deionized water is 1:3; choose FA / O chelating agent to adjust the pH value to 13; choose JFC as surface active agent, the content is 100ml / l; choose H 2 o 2 It is an oxidant with an oxidant content of 10ml / l. The polishing process conditions are: flow rate 5L / min, temperature 30°C, speed 120rpm / min, pressure 250g / cm 2 .

Embodiment 3

[0034]Preparation of polishing liquid: choose 30L silica sol with a particle size of 15nm as abrasive, the concentration is 20%, and the ratio of deionized water is 1:2; select FA / O chelating agent to adjust the pH value to 12.5; select FA / O activity A kind of surfactant, JFC, fatty alcohol polyoxyethylene ether, polyoxyethylene alkylamine, alkyl alcohol amide, the content is 50ml / l; choose H 2 o 2 It is an oxidizing agent with an oxidizing agent content of 20ml / l. The polishing process conditions are: flow rate 3L / min, temperature 25°C, speed 90rpm / min, pressure 200g / cm 2 .

[0035] After measurement, the flatness of the surface of the copper wire after polishing by the method of the present invention is less than 0.5nm. see figure 1 , when the abrasive concentration>20wt%, the number of sags decreased significantly.

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Abstract

A method for controlling the level degree on the ULSI multi-layer wiring in chamico-mechanical polishing includes such steps as diluting SiO2 hydrosol by deionized water, adding metal ion chelating agent to regulate pH=10-13, adding alcohol-ether kind of surfactant and oxidant while stirring to obtain polishing liquid, and polishing at 20-40 deg.C and 60-120 rpm under 100-250 g / sq.cm.

Description

technical field [0001] The invention relates to integrated circuit chemical mechanical planarization technology, in particular to a method for controlling the flatness of ULSI multilayer copper wiring chemical mechanical polishing. Background technique [0002] Currently, global and local planarity are very important in chemical mechanical polishing of ULSI multilayer copper wiring. On an 8-inch chip, 13.44% loss may be caused only by sag (including edge sag and line sag, especially metal lead sag) or dish-shaped pits. With the development of the substrate size from Φ200mm to Φ300mm, the influence of the polished surface flatness on the surface state of the polished copper wire is increasing. The surface roughness directly affects the wiring of the next layer of copper, affects the breakdown characteristics of the circuit, the interface state and the lifetime of the minority carrier, and is directly related to the performance quality and yield of IC devices. However, if th...

Claims

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Application Information

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IPC IPC(8): B24B29/02C09G1/02C09G1/04
Inventor 刘玉岭刘博
Owner 天津河北工业大学资产经营有限责任公司
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