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Negative nano-imprinting method

A nano-imprinting and negative-type technology, which is applied in the manufacture of electrical components, semiconductor/solid-state devices, circuits, etc., can solve problems such as easy-to-produce defects, and achieve the effects of easy control, avoiding stripping process, and low price

Inactive Publication Date: 2006-07-12
国家纳米技术产业化基地
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Due to the limitation of the principle of the stripping process, it is easy to produce defects

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] Embodiment 1: a kind of negative type nano imprinting method is characterized in that it is made of following steps (see figure 2 ): (1) first vapor-deposit metal film layer 15 on silicon substrate 1, and spin-coat photoresist 2 on metal film layer 15 (see figure 2 -a); (2) the nano-pattern of the template 3 is copied to the photoresist 2 under heat and pressure conditions (see figure 2 -b), (3) and transfer the pattern to the metallized film layer I5 with reactive ion etching technology (see figure 2 -c); (4) then use the pattern of photoresist 2 as a mask to etch the bare metal I5 that is not covered by photoresist 2 (see figure 2 -d); (5) making metal nanostructures.

[0033]The metal nanostructure that above-mentioned step (5) makes obtains single metal nanostructure by directly dissolving photoresist 2 with organic solvent (see figure 2 -e).

Embodiment 2

[0034] Embodiment 2: a kind of negative type nano imprinting method is characterized in that it is made of following steps (see figure 2 ): (1) first vapor-deposit metal film layer 15 on silicon substrate 1, and spin-coat photoresist 2 on metal film layer 15 (see figure 2 -a); (2) the nano-pattern of the template 3 is copied to the photoresist 2 under heat and pressure conditions (see figure 2 -b), (3) and transfer the pattern to the metallized film layer I5 with reactive ion etching technology (see figure 2 -c); (4) then use the pattern of photoresist 2 as a mask to etch the bare metal I5 that is not covered by photoresist 2 (see figure 2 -d); (5) making metal nanostructures.

[0035] The metal nanostructure that above-mentioned step (5) makes is by using the pattern of photoresist 2 as mask evaporation metal II6 (see figure 2 -f), then remove the photoresist 2 with an organic solvent to prepare a double metal nanostructure (see figure 2 -g).

Embodiment 3

[0036] Example 3: Preparation of SiO by Combining Direct Write Electrotechnical Beam Exposure Technology and Reactive Ion Etching Technology 2 / Si template, the line width, period and height of the template pattern are 170nm, 370nm and 130nm respectively. Take a 2×2cm silicon wafer, after cleaning, vapor-deposit a 25nm thick gold film, then spin-coat photoresist on the surface of the gold film, dry it at 170°C, and the thickness will be 150nm, and then copy the nanometer pattern on the template to the On photoresist (imprint conditions: 190°C, 45bar, 3min). The redundant photoresist in the groove is removed by reactive ion etching process, and the nanometer pattern is transferred to the surface of the gold film. Then use the photoresist nanopattern as a mask, and use KI / I 2 solution (0.0025M I 2 +0.015M KI) to dissolve the exposed gold film for 40s, and then remove the photoresist with hot acetone under ultrasonic conditions to obtain a gold nanostructure with a line width ...

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Abstract

The invention discloses a negative-type nanometer stamping method, which comprises the following steps: (1) depositing metallized film I on the silicon base; hanging to coat the photo-etching glue on the metallized film I; (2) duplicating the mould plate nanometer pattern to the photo-etching glue in the heating and pressurizing condition; (3) transferring the pattern to the metallized film I through reaction ionic etching technique; (4) adapting photo-etching glue as mask to corrode the uncovered naked metal l; (5) preparing the metal nanometer structure. The invention avoids the traditional striping craft of nanometer stamping technique to produce smooth line metal structure, which reduces the cost and simplifies the control wire breadth through corrosion condition and time adjustment as well as prepares double-metal structure with deposited second metal after chemical corrosion.

Description

(1) Technical field: [0001] The invention relates to a nano-imprinting technology, in particular to a negative nano-imprinting method applied in the preparation of metal nanostructures. (two) background technology: [0002] According to the 2003 edition of the International Semiconductor Technology Roadmap, the feature size of devices will reach below 70 nanometers around 2008. At that time, the current optical lithography technology will approach its technical limit due to the limitations of photoresist, mask material and light source. If this technical barrier cannot be overcome, integrated circuits will not be able to continue to shrink. Therefore, the new generation of nanostructure processing technology become a research hotspot. Starting from fundamental development principles, new technological approaches must strike a balance between size, speed, functionality, and cost. Technical researchers in the semiconductor industry have made a series of difficult improvement...

Claims

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Application Information

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IPC IPC(8): G03F7/20H01L21/027
Inventor 谢国勇焦丽颖刘忠范张锦
Owner 国家纳米技术产业化基地
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