Bias voltage applying circuit and semiconductor memory device

Abstract

Two bias circuits (20) which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element (21a, 21b) between a power supply node Vcc and a junction node (Nca, Ncb), where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element (22a, 22b) between the power supply node and an output node (Nouta, Noutb), where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element (23a, 23b) and a fourth active element (24a, 24b) between the junction node and a current supply node Nsa (Nsb) and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

Description

technical field [0001] The present invention relates to a semiconductor memory device, and more specifically, to a readout technique for detecting a current flowing in a memory cell of the semiconductor memory device and determining its memory state at high speed. Background technique [0002] In a semiconductor memory device, various methods are used to read the memory state of its memory cells. A flash memory which is one of nonvolatile semiconductor memory devices will be described as an example. The flash memory is configured such that each memory cell has a memory transistor having a floating gate structure, and stores information based on the accumulated charge (electron) injected into the floating gate of each memory cell. Specifically, in a state where many electrons are injected into the floating gate, it is difficult to form an inversion layer in the channel region, so the threshold voltage of the memory cell becomes high (defined as a program ...

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Problems solved by technology

[0009] However, in Figure 9 In the bias voltage applying circuit of the conventional example 2 shown, since an additional stage of the select transistor 200 is required for switching the left and right bit lines, and an additional resistance component is added to the memory cell current path, the bit The CR (capacitance-resistance product) of the line increases and the transition characteristics deteriorate, becoming the main factor hindering high-speed readout

[0010] In addition, in Figure 10 In the bias voltage applying circuit of the conventional example 3 shown, the Vds (voltage between the drain and the source) of the PMOS switching transistor 300 is approximately 0V, so the on-resistance thereof becomes high, and the PMOS voltage of the load circuit 103 It takes time before the gate potential becomes equal to the drain potential

Therefore, in the meantime, since the current mirror does not work properly, it becomes a major factor hindering high-speed readout

[0011] In addition, the load circuit 103 of any of the bias voltage applying circuits of the conventional examples 2 and 3 is asymmetrical, so a difference is generated in the load capacitance of the input node of the sense amplifier of the next stage, and there is a transient response characteristic caused by the correlation Dangers that hinder high-speed readout from different

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