Improved mask ROM process and element

A read-only memory, mask-type technology, applied in electrical components, electrical solid-state devices, semiconductor devices, etc., can solve the problems of the initial voltage drop of memory cells, improper reading of memory cells, etc., to achieve high component yield, easy effect used

Inactive Publication Date: 2004-01-14
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The initial voltage of the memory cell drops and causes improper readout of the memory cell
These and other limitations are often present in traditional ROM integrated circuit components

Method used

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  • Improved mask ROM process and element
  • Improved mask ROM process and element
  • Improved mask ROM process and element

Examples

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Embodiment Construction

[0015] The present invention provides techniques including methods of manufacturing semiconductor elements. More specifically, the present invention provides a method for manufacturing a masked ROM, which can reduce its critical dimension and effectively avoid the breakdown effect. However, the scope of application of the present invention is wider than this. For example, the present invention can be applied to the design of embedded ROM and other aspects.

[0016] FIG. 1 shows a top view 100 of a masked ROM cell design in accordance with an embodiment of the present invention. This figure is only an example and should not be used to limit the scope of this patent application. Any person skilled in the art will understand that the present invention can have many other variations, modifications and applications. As shown, the top view includes a plurality of polysilicon conductors 107 each defining a word line for a memory cell array 101 . Source / drain regions or active reg...

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PUM

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Abstract

The invention discloses a process for making integrated circuit elements of masking type read-only memory comprising, carrying out a implanting process to form a wellblock on the semiconductor substrate, and forming a plurality of embedded implanting area through the first pattern type light shield, each of the embedded implanting area includes a source electrode area and drain area of the individual memory element area, which belongs to one of the plurality of memory elements. The invention can also be used to form pocket areas in the embedded implanting area of the individual memory element area.

Description

technical field [0001] The present invention relates to integrated circuits and their processes in the manufacture of semiconductor components. More specifically, the present invention provides a method for manufacturing a masked ROM, which can reduce its critical dimension and effectively avoid the breakdown effect. However, the scope of application of the present invention is wider than this. For example, the present invention can be applied to the design of embedded ROM and other aspects. Background technique [0002] Integrated circuits have evolved from a handful of connected elements originally fabricated on a silicon wafer to today's millions of elements. Traditional integrated circuits offer performance and complexity far beyond what was originally imagined. To improve complexity and circuit density (ie, the number of components that can fit on a chip), the minimum component size, known as component "geometry", has been getting smaller and smaller with each genera...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/265H01L21/336H01L21/8246H01L27/112H01L29/10
CPCH01L27/1126H01L29/66537H01L29/1045H01L27/112H01L21/26586H01L29/66583H10B20/383H10B20/00
Inventor 陈国庆李若加
Owner SEMICON MFG INT (SHANGHAI) CORP
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