Six-stage pipeline processor based on RISC-V instruction set
A RISC-V, pipeline technology, applied in the direction of concurrent instruction execution, machine execution device, climate sustainability, etc., can solve the problem of low processor performance
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[0039]The following describes in detail the embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary, and are intended to explain the present invention and should not be construed as limiting the present invention.
[0040] see Figure 1 to Figure 7 , the present invention provides a six-stage pipeline 1 architecture based on the RISC-V instruction set:
[0041] It includes a six-stage pipeline 1, a first register 2, a data memory 3 and an instruction memory 4. The six-stage pipeline 1 includes an instruction fetch module 11, a decoding module 12, a distribution module 13, a transmission module 14, an execution module 15 and a write back Module 16, the instruction fetch module 11, the decoding module...
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