Processor device, instruction execution method thereof and computing equipment

Abstract

The embodiment of the invention discloses a processor device, an instruction execution method thereof and computing equipment. The apparatus comprises one or more single-instruction multi-thread processing units, and the single-instruction multi-thread processing units comprise one or more thread bundles used for executing instructions; a shared register group including a plurality of general purpose registers shared among the thread bundles; a predicate base address register which is arranged corresponding to each thread bundle and is used for indicating a base address of a group of general purpose registers which are used as predicate registers of each thread bundle in the shared register group; wherein each thread bundle performs asserted execution on instructions based on predicate values in the set of general purpose registers used as predicate registers for each thread bundle. According to the embodiment of the invention, the inherent special predicate register of each thread bundle in the original processor architecture can be canceled, the dynamic expansion of the predicate register resource of each thread bundle is realized, the full utilization of processor resources is realized, the overhead of switching instructions is reduced, and the instruction processing performance is improved.

Description

technical field [0001] The present application relates to the technical field of processors, and in particular, to a processor device, an instruction execution method thereof, and a computing device. Background technique [0002] At present, single-instruction multi-thread processing (SIMT) cores are usually used in multi-core processing chips such as CPUs and GPUs. The single-instruction multi-thread processing (SIMT) cores can have multiple basic units for executing instructions, called warps of threads (WARP). The size of the warp dictates the number of parallel threads for Single Instruction Multiple Threading. Each warp usually includes a variety of special-purpose registers, among which the predicate (Predicate) register is a key control method for implementing efficient branch instructions in the GPU. In NVIDIA's chip instruction system, usually a thread warp has 32 parallel threads (Thread), each thread warp has seven 32-bit Predicate registers P0-P6, each Predicate...

AI Technical Summary

Problems solved by technology

[0003] However, the inventors of the present application found that in the current GPU chip system, the predicate registers corresponding to each warp are fixed and the number is too small, resulting in In complex scenarios, such as complex IF-ELSE nesting and Switch-Case branch condition instructions, predicate registers are not enough; and when resources are limited, each warp can still only use 7 predicate registers, and the remaining resources cannot fully utilized

In addition, the predicate registers of each warp cannot be shared between multiple warps, and the existing mechanism will also cause a loss of system performance, requiring more instructions to be executed to achieve the desired function.

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