Excitation data block processing method for hardware accelerator and hardware accelerator

Abstract

The invention discloses an excitation data block processing method for a hardware accelerator and the hardware accelerator, and the method comprises the steps: 1) enabling an AI hardware accelerator to divide a convolution layer into a shallow convolution layer and a deep convolution layer when the AI hardware accelerator carries out the parallel calculation of a convolution network; 2) partitioning a shallow convolutional layer by an AI hardware accelerator; 3) enabling the AI hardware accelerator to calculate the blocked shallow convolutional layer; and 4) enabling the AI hardware accelerator to combine results obtained after calculation of all the shallow convolutional layers is completed and then take the results as input data of a deep convolutional layer, and carrying out deep convolutional layer calculation. The hardware accelerator shares the excitation data storage unit and the register array, the hardware accelerator performs block parallel processing on excitation data of the convolutional neural network, and stores the segmented excitation data in the shared excitation data storage unit, so that the out-of-chip data access of the excitation data of the hardware accelerator is zero. According to the invention, the off-chip data access is 0, and the on-chip SRAM resource demand of the AI accelerator is greatly reduced.

Description

technical field [0001] The present invention relates to the technical field of digital signal processing, in particular to the field of hardware accelerator design methods, in particular to a hardware accelerator excitation data block processing method and the hardware accelerator. Background technique [0002] In the fields of artificial intelligence and parallel computing, there are a large number of multidimensional matrix operations. In order to achieve real-time signal processing, AI hardware accelerators usually integrate multiple parallel computing units to perform parallel computing on data to achieve fast inference computing. How to achieve efficient parallel computing through a hardware platform with parallel computing capabilities is a major difficulty in the design of AI hardware accelerators. The main difficulty lies in: the energy consumption of data reading, especially the reading of off-chip DRAM data is much higher than that of addition, Energy consumption ...

AI Technical Summary

Problems solved by technology

Due to the large cache required for the incentive data during the inference calculation process of the convolutional network hardware, the on-chip calculation cannot be realized on the limited on-chip SRAM of the AI ​​hardware accelerator at present, and the off-chip data access of the incentive data is reduced to zero. Greatly affects the efficiency and power consumption of the system

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