Layout-based high fan-out line network optimization method and optimization system for FPGA integrated circuit

Abstract

The invention provides a layout-based high fan-out line network optimization method and system for an FPGA integrated circuit, each line network comprises a plurality of connecting lines connected between a driving device and a plurality of output devices, and the optimization method comprises the following steps: marking time sequence criticality at the output ends of the plurality of connecting lines respectively; respectively setting a cluster control parameter for each time sequence criticality; obtaining the time sequence criticality of the wire net, and judging whether the wire net is a high fan-out wire net needing to be split or not according to the cluster control parameters; splitting the plurality of output devices into a plurality of clusters according to the cluster control parameters by adopting a clustering algorithm for the network needing to be split; copying the plurality of copies based on the driving devices, and assigning to the plurality of clusters as the driving devices therein. According to the optimization method and system, the time sequence criticality is defined, the cluster control parameters are set according to the time sequence criticality, the network is split based on the parameters, the association degree in the cluster is high, the device transmission performance is improved, the algorithm is accurate and rapid, the splitting efficiency is improved, the cost is reduced, and the network layout is simplified.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a layout-based high fan-out network optimization method and an optimization system for FPGA integrated circuits. Background technique [0002] FPGA (Field Programmable Gate Array, Programmable Logic Gate Array) is a logic device composed of many logic units. It has abundant hardware resources and powerful parallel processing capabilities, and has been widely used in many fields such as data processing and communication. After the physical position of the logic unit is determined in the FPGA integrated circuit, the actual physical connection of the signal line to the connection relationship of the logic unit needs to be established between the drive device and the output device. If the fan-out of the network is too high , that is, the driving device needs to drive too many output devices, so the line network will be particularly complicated. A wire net with a larger fanout usua...

AI Technical Summary

Problems solved by technology

[0003] The optimization method of the high fan-out net that has been applied at present is to divide the output devices of the high fan-out net into multiple groups according to the similar layout positions, and insert registers in each group to drive multiple output devices to reduce the load of the net. The division method is too single, and the timing impact between each device is not considered, and the performance of the devices in each group is poor after grouping

Therefore, the current optimization method for high fan-out nets has great limitations and cannot meet the needs of integrated circuits with high integration and fast signal processing.

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