Timing correction method and device, computing device and storage medium

Abstract

The invention discloses a timing correction method and device, computing device and storage medium applied to integrated circuits. According to the timing correction method of the embodiment of the present invention, the integrated circuit includes a plurality of common logic units and a plurality of spare correction units; in the integrated circuit, determine the timing path with a timing problem and the first common logic unit in the timing path that does not meet the timing requirements ; Set a search range around the first common logic unit, and determine at least one spare correction unit that can be used for timing correction within the search range; test one by one and obtain at least one spare correction unit that can be used for timing correction. Used in integrated circuits Timing result: determining a target spare correction unit for timing correction of the integrated circuit according to the timing result, where the target spare correction unit is at least one of at least one spare correction unit available for timing correction. According to the timing correction method and the like in the embodiments of the present invention, the correctness of chip design is ensured.

Description

technical field [0001] The present invention relates to the technical field of electronic design automation (EDA), in particular to a timing correction method and device, a computing device and a storage medium. Background technique [0002] In digital integrated circuit design, in order to ensure that the chip can work normally and achieve the expected frequency, it is necessary to check whether the time when the clock signal and data signal arrive at the register synchronization unit meets the constraints of setup time and hold time. If timing violations are found, the RTL code can be re-modified early in the design; however, engineering changes ECO are required to fix the timing issues later in the design. [0003] Generally, the ECO correction timing can be divided into two categories: pre-mask and post-mask. Pre-mask ECO is more flexible. When timing problems are found before tape-out, common methods such as buffer cell insertion, cell size change, and large line netwo...

AI Technical Summary

Problems solved by technology

If a timing violation is found, the RTL code can be re-modified early in the design; however, later in the design, an engineering change ECO is required to fix the timing issue

Images