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Soc PMUT, array chip and manufacturing method suitable for high-density system integration

A technology of system integration and manufacturing method, which is applied to components of TV systems, manufacturing microstructure devices, fluid velocity measurement, etc., can solve the problem of reducing PMUT unit duty cycle, affecting PMUT array uniformity, operating frequency, and poor power consumption Influence and other problems, to achieve the effect of reducing chip size and system volume, realizing one-machine multi-frequency scanning, and high-density system integration

Active Publication Date: 2022-04-19
NANJING SHENGXI XINYING TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As a result, metal routing faces two major constraints
First, if you want each cell to have its own independent top-level metal connection, as shown in Figure 2(b), you must add an additional amount of metal routing
As a result, the metal wiring reduces the duty cycle of the PMUT unit (the ratio of the area that can generate ultrasound in the unit to the entire unit area), and the metal wiring takes up a large proportion of the chip area outside the array at the same time, and the parasitics generated by the additional metal wiring Resistors, Capacitors, have adverse effects on speed, power consumption, etc.
Second, the design of most PMUT arrays today, in order to reduce additional metal wiring, shares the same top-level metal connection (common column connection) with multiple cells in the same column. As a result, the mutual interference (cross-talk) of these cells becomes serious, the main performance parameters of the PMUT array, such as effective frequency bandwidth, signal-to-noise ratio, etc., are adversely affected
The chip area occupied by the metal wiring is much larger than the chip area occupied by the PMUT array, which is extremely uneconomical
At the same time, the longer metal wiring length increases the parasitic effect of resistors and capacitors, which has a negative impact on the operating frequency and power consumption of the PMUT array.
The uneven length of the wiring will also directly affect the uniformity of the work of the PMUT array

Method used

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  • Soc PMUT, array chip and manufacturing method suitable for high-density system integration
  • Soc PMUT, array chip and manufacturing method suitable for high-density system integration
  • Soc PMUT, array chip and manufacturing method suitable for high-density system integration

Examples

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Effect test

Embodiment 1

[0091] As shown in Fig. 4 (a), 4 (b), present embodiment provides a kind of SOC PMUT suitable for high-density system integration, comprises first wafer and second wafer, and first wafer arranges silicon substrate material 160 , CMOS unit 160-CMOS with double-layer metal wiring, the second wafer arranges the mechanical layer 130, the lower metal layer 112, the piezoelectric material layer 115, the upper metal layer 114, the cavity body 120, and the CMOS auxiliary circuit of the double-layer metal wiring 300-CMOS.

[0092] The two ends of the metal interconnection layer 201 of the CMOS unit 160 -CMOS disposed above the silicon substrate 160 are vertically interconnected with two second-layer metal wirings 202 above the metal interconnection layer 201 through two metal lead holes 212 respectively. The silicon substrate 160 is provided with two silicon through-hole TSVs 162 that run through the entire silicon substrate 160, so that the two ends of the metal interconnection layer ...

Embodiment 2

[0103] This embodiment provides a SOC ultrasonic transducer suitable for high-density system integration, which is similar to the structure of Embodiment 1. Considering the overall design of the SOC PMUT, when the resolution requirement is high and a large-scale array is required, the interconnection Implementations may require multiple layers of wiring. For example, when artificial intelligence algorithms are also put into SOC PMUT ultrasonic design, CMOS IC design may require 5-6 layers of metal wiring. In the process flow of the present invention, the wiring structure has been specially considered, and the process flow has great flexibility in the number of wiring layers. Therefore, in this embodiment, on the basis of the first embodiment, at least one layer of metal wiring is provided above the second layer of metal wiring, and the metal wiring of each layer of the at least one layer of metal wiring is vertically interconnected through metal lead holes. , the lowermost la...

Embodiment 3

[0106] This embodiment provides a vertical electrical interconnection to replace the traditional planar wiring method to manufacture the ultrasonic transducer suitable for high-density system integration. The SOC PMUT ultrasonic transducer vertically connects the PMUT upper metal layer 114 to the stop layer metal structure 303 and the corresponding CMOS auxiliary circuit 300-CMOS second layer metal 302 respectively through the upper metal connection hole ZTM163-1; The lower metal layer 112 is vertically connected to the stop layer metal structure 303 and the corresponding CMOS auxiliary circuit 300-CMOS second layer metal 302 through the lower metal connection hole ZBM 163-2, and then through the two metal The lead hole 312 is vertically connected to any device in the CMOS auxiliary circuit 300-CMOS. Through reasonable wiring, series and parallel connection of multiple ultrasonic transducers can be realized.

[0107] The CMOS auxiliary circuit 300-CMOS can be connected to the...

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PUM

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Abstract

The invention discloses a SOC PMUT suitable for high-density system integration, an array chip and a manufacturing method. The SOC PMUT suitable for high-density system integration is directly bonded to an active wafer, and has a multi-channel metal wiring structure in a vertical direction. Realize the vertical stacking of SOC PMUT array and its CMOS auxiliary circuit, monolithic integration, and extend to the packaging level through TSV, no longer need to communicate with CMOS through the pads around the array, and relieve the metal interconnection of traditional ultrasonic transducers The bottleneck greatly reduces the chip area occupied by the metal interconnection of the ultrasonic transducer, and at the same time reduces the length of the metal wiring, and the resulting electrical parasitic effects have a negative impact on the performance of the ultrasonic transducer array.

Description

technical field [0001] The invention relates to the technical field of high-density single-chip integrated semiconductor sensors, in particular to a new structure and processing technology for integrating a 3D (3dimensional) three-dimensional PMUT framework and an SOC (System-On-Chip). Background technique [0002] Ultrasonic diagnostic instrument, through its ultrasonic probe, emits ultrasonic waves to the human body, and uses various information generated by the reflection, refraction, and diffraction of sound during the propagation process of human organs and tissues to receive, amplify, and transmit information. processed to form an image or flow Doppler and finally displayed on a monitor. A medical color ultrasonic diagnostic instrument mainly includes: probe, host, control panel, display and other accessories. [0003] As human society enters the era of big medical care, the application of medical ultrasound has developed rapidly. From medical imaging, such as fetal ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): B81B7/00B81B7/02B81C1/00B06B1/06
CPCB81B7/008B81B7/007B81B7/02B81C1/00238B81C1/00301B81C1/00246B06B1/06B81B2201/0271H01L24/80H01L24/94H01L23/481H01L25/0657H01L24/08H01L2224/08145H01L2224/80895H01L2224/80896H01L2224/80365H01L2225/06527H01L2225/06558H01L2225/06565H01L25/50H01L2225/06541H01L23/3171H01L21/76898A61B8/4483B06B1/0629H10N30/8554H10N30/082H10N30/076B81B2207/012B81B2207/07B81C2203/0785H01L2924/1461
Inventor 李晖尹峰
Owner NANJING SHENGXI XINYING TECH CO LTD
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