Power transistor structure and manufacturing method thereof

Abstract

The invention relates to a power transistor structure and a manufacturing method thereof, and the structure comprises a drain electrode substrate which is provided with a processing surface provided by a drain electrode epitaxial layer and a corresponding back surface, wherein a plurality of first grooves are formed in the processing surface side by side, and grids are disposed in the first grooves; an active layer formed in the drain electrode epitaxial layer; an inner dielectric layer formed in the first groove on the grid electrode in a breaking manner, so that the grid electrode is of an embedded structure and is electrically isolated from the source electrode layer; second grooves which are formed at openings of the first grooves, so that concave areas on the two sides of the openings of the first grooves and mesa areas between the second grooves are formed, heavily doped parts are formed on the two sides of the inner dielectric layer in the concave areas, and heavily doped isolation layers are formed in the mesa areas; a source layer disposed on the mesa region of the active layer and conductively connected to the heavily doped portion through the recessed region; and an active layer which forms a longitudinal channel below the heavily doped part and at two sides of the grid electrode. The method has the effects of keeping high current leakage prevention performance and providing higher current passing capacity.

Description

technical field [0001] The present application relates to the field of semiconductor transistors, in particular to a power transistor structure and a manufacturing method thereof. Background technique [0002] As the key and important device of the semiconductor chip, the field effect transistor structure has a variety of structures, mainly including the following types: FinFET fin field effect transistor, JFET junction field effect transistor, surface field effect transistor and tunneling field effect transistor. transistor. Regardless of the transistor structure, the source contact and the drain contact are designed on the same surface of the semiconductor substrate. With the development of the trend of wafer thinning and device miniaturization, how to ensure the anti-leakage current performance? Passing a large current will become more and more a problem that needs to be faced and overcome. [0003] Among them, the JFET junction field effect transistor and the tunneling...

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Problems solved by technology

[0003] Among them, the JFET junction field effect transistor and the tunneling field effect transistor, because the channel layer is designed in the active area of ​​the semiconductor substrate, and the source layer is formed on the active area, the FinFET fin transistor is the channel layer. The channel layer is designed on the protruding fin-shaped gate by means of additional deposition, and the carriers flow laterally between the integrated source and the integrated drain through the channel, but this design requires the source layer and the active An internal dielectric layer is provided between the source layers to prevent adverse effects on the conductivity of the active layer during the source process. However, the source layer is usually made of metal materials, which have poor connection with the internal dielectric layer. When the semiconductor substrate is stressed, it is prone to delamination and fracture, resulting in poor contact

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