Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The forming method comprises the steps of providing a substrate, and forming a to-be-etched layer on the substrate, forming a core layer and a plurality of sacrificial layers located in the core layer on the to-be-etched layer, and enabling the sacrificial layers to be arranged at intervals, removing part of the core layer between the adjacent sacrificial layers to form a first groove penetrating through the core layer, and exposing the sacrificial layers from the side wall of the first groove, carrying out first ion doping treatment on the core layer of the side wall of the first groove, wherein the first ion doping treatment is suitable for increasing the etching resistance of the core layer of the side wall of the first groove, forming a side wall on the side wall of the first groove, after first ion doping processing and side wall forming are carried out, removing the sacrificial layer, forming a second groove penetrating through the core layer, and isolating the second groove and the first groove by a side wall, and etching the to-be-etched layers at the bottoms of the first groove and the second groove by taking the core layer and the side walls as masks. According to the embodiment of the invention, the probability that the core layer on the side wall of the first groove is mistakenly etched in the step of removing the sacrificial layer is reduced.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] With the rapid growth of the semiconductor integrated circuit (IC) industry, semiconductor technology continues to move towards smaller process nodes driven by Moore's Law, making integrated circuits smaller in size, higher in circuit precision, and in circuits. The direction of higher complexity. [0003] In the development of integrated circuits, as the functional density (ie, the number of interconnect structures per chip) gradually increases, the geometric size (ie, the smallest component size that can be produced by process steps) also gradually decreases. Accordingly, the difficulty and complexity of integrated circuit fabrication are increased. [0004] At present, with the continuous shrinking of technology nodes, how to improve the matching de...

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Problems solved by technology

[0003] During the development of integrated circuits, usually as the functional density (that is, the number of interconnection structures per chip) gradually increases, the geometric size (that is, the minimum component size that can be produced using process steps) also gradually decreases. Correspondingly increases the difficulty and complexity of integrated circuit manufacturing

[0004] At present, in the case of shrinking technology nodes, how to improve the matching degree between the pattern formed on the wafer and the target pattern has become a challenge

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