Dynamic self-adaptive SOPC fault-tolerant method based on task levels

Abstract

The invention provides a dynamic self-adaptive SOPC fault-tolerant method based on task levels, which is used for solving the technical problems of low user availability and low resource utilization rate in the prior art, and comprises the following implementation steps: constructing a dynamic adaptive programmable system-on-chip; internally configuring an access port ICAP to load a global bit stream of a task to the FPGA; enabling the FPGA to perform region division; acquiring the number of particle overturn signals in the static region; enabling the PS end to evaluate the task level; enabling the PS end to send configuration information to the ICAP; enabling the ICAP to load a part of bit streams to the dynamic reconfigurable region; enabling the reconfigurable module to execute the task; enabling the PS end to judge whether the reconfigurable module breaks down or not; and enabling the ICAP to load a part of bit streams to the fault reconfigurable module. According to the method, the task execution time, the task execution deadline and the fault repair time are used as task grading bases, so that the method has relatively high user availability and resource utilization rate.

Description

Technical field[0001]The invention belongs to the technical field of intelligent fault-tolerant systems, and relates to a dynamic adaptive SOPC fault-tolerant method, in particular to a dynamic adaptive programmable system-on-chip SOPC fault-tolerant method, which can be applied to the critical system-on-chip fault-tolerant design of space high radiation and spaceborne environment.Background technique[0002]System On Chip (SOC, System On Chip) is an embedded system that completes the main logic functions by a single chip. Programmable System On Chip is an embedded system based on SOC and has Field Programmable Gate Array (FPGA, Field Programmable Gate Array). ) Special embedded system with flexible design method. Because SOPC has the ability of software and hardware cooperative system programming, it is widely used in space and spaceborne high-performance, high-reliability computing systems.[0003]SOPC includes programmable logic PL end Programmable Logic realized by FPGA and processo...

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Problems solved by technology

[0007] For example, the application publication number CN 111338833 A, titled "A Dynamic Adaptive SRAM FPGA System Fault Tolerance Method Based on BRAM Detection", discloses a dynamic adaptive SRAM FPGA system fault tolerance method based on BRAM detection, which can According to the situation of the radiation environment, calculate the different redundant structures of the single event turnover rate adjustment system to improve the reliability of user tasks, but its disadvantage is that it only depends on the external environment radiation to adjust the redundant structure, and does not consider the execution of user tasks time, fault repair time, and task execution deadlines, resulting in low user availability and resource utilization

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