A Genetic Algorithm Based Test Stimulus Generation Method for Catalog Controller

Abstract

The invention discloses a method for generating test incentives for a directory controller based on a genetic algorithm. The invention includes: S1: performing symbolic coding of the genetic algorithm for the test characteristics of the directory controller; S2: creating a first-generation population of test incentives based on negative selection The algorithm selects random chromosomes to join the population; S3: Perform mutation operations to generate new chromosomes, and join the population based on the negative selection algorithm; S4: Perform crossover operations to generate new chromosomes, and join the population based on the negative selection algorithm; S5: Repeat steps S3-S4 until reaching the maximum heredity Chromosomes with a fitness value greater than or equal to the set threshold in algebra or occurrence. The present invention can excavate the relationship between the coverage rate and the stimulus input, guide the generation of random test stimulus, and supervise the selection of new chromosomes to join the population according to the negative selection algorithm, so as to achieve the least redundant test stimulus and cover different coverage rate function points as soon as possible. Reduce test time and improve verification efficiency.

Description

A method for generating test incentives for catalog controllers based on genetic algorithm technical field The present invention relates to chip design technology, be specifically related to a kind of catalog controller test excitation generator based on genetic algorithm into method. Background technique On-chip multi-core processor (CMP, Chip Multi-processors) has become the direction of processor development, with With the increasing demand for data communication between multi-core and multi-threads, on-chip large-capacity Cache (cache) is integrated to realize data Share and interact, thereby reducing memory fetch latency and reducing access conflicts. A 64-core processor, as shown in Figure 1, uses a CMP junction architecture, including processor core (core), Cache, Network on Chip (NoC), directory controller (Directory Control Unit, DCU), storage controller (Memory Control Unit). In Figure 1, Core is the CPU Core, completes the scheduling and execution of...

AI Technical Summary

Problems solved by technology

Writing test vectors manually takes a lot of time and labor costs, and sometimes it is difficult to meet the large number of test vectors with wide coverage required by regression testing; random test vectors, the size and length of the generated test vectors are flexible and controllable, but the test vectors are easy Repeated coverage, in order to reduce the generation of redundant incentives and accelerate the convergence of functional verification, the random test generation method driven by coverage feedback is the current research hotspot of random test generation technology

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