Silicon-based semiconductor pn junction structure and its preparation method, photocathode and application
A semiconductor and PN junction technology, which is applied in the field of silicon-based semiconductor PN junction structure and its preparation, can solve the problems of complex preparation process and high cost of PN junction, and achieve the effect of improving separation efficiency, excellent stability and strong controllability
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Embodiment 1
[0035] (1) Silicon wafer cleaning
[0036] Place the p-Si single crystal (100) silicon chip in the HF solution with a volume concentration of 1% and soak for 15s, rinse it with deionized water, N 2 Blow dry; this step can remove the SiO produced by self-oxidation on the surface of p-Si single crystal (100) silicon wafer 2 ;
[0037] (2)TiO 2 Preparation of anatase nanolayers
[0038] Will N 2 The blow-dried p-Si single crystal (100) silicon wafer is placed in the chamber of the atomic layer deposition system for deposition. The precursors are tetraisopropyl titanate and water to achieve the deposition of TiO on the surface of the p-type silicon substrate. 2 Nanocrystalline layer; the deposition temperature of atomic layer deposition is 270 ° C, the number of atomic layer deposition cycles is 850, TiO2 The nanocrystalline layer was deposited with a thickness of 26 nm.
[0039] (3) TiO 2 Anatase Nanolayer Reduction
[0040] The encapsulated p-Si / TiO 2 The heterojunction ...
Embodiment 2
[0047] Carry out preparation and reaction with embodiment 1 method, its difference is only that in step (2) atomic layer deposition cycle number is 350, TiO 2 The thickness of the nanocrystalline layer is 10nm.
Embodiment 3
[0049] Carry out preparation and reaction with embodiment 1 method, its difference is only in step (2) in atomic layer deposition cycle number 1200,, TiO 2 The thickness of the nanocrystalline layer is 36nm.
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