1588 synchronization method, system and device for high-speed TTE cascade network

Abstract

The invention belongs to the technical field of network communication. The invention discloses a 1588 synchronization method, a 1588 synchronization system and a 1588 synchronization device for a high-speed TTE cascade network. The 1588 synchronization method comprises steps of enabling a port to calculate link delay; enabling a switching node to receive data frames, stamping receiving timestamps,analyzing the synchronous frame Sync and extracting the frame content; caching timestamp information, calculating time deviation, correcting a local clock, forwarding a synchronization frame Sync toa sending port, sending arbitration, sending analysis and caching a frame type, performing MAC sending processing, taking a sending timestamp, extracting the cached sending frame type, modifying a Sync frame correction domain, and finishing transparent transmission. According to the invention, the data frame type is analyzed at the data link layer and then MAC sending processing is carried out, sothat timestamp correction can be carried out rapidly when a synchronization frame is about to be transmitted to a high-speed network port; and meanwhile, the switching node is designed to adopt a transparent clock and common slave clock working mode, so that the universality and functional diversity of a synchronization scheme are improved.

Description

technical field [0001] The invention belongs to the technical field of network communication, and in particular relates to a high-speed TTE cascaded network 1588 synchronization method, system and device. Background technique [0002] At present, time-triggered Ethernet is a time-deterministic network compatible with standard Ethernet. By adding a time-triggered method on the basis of traditional Ethernet, it provides a conflict-free and deterministic network for key control data services. transfer method. With the increase of time-triggered Ethernet data traffic, the network rate continues to increase, and the number of network terminals is gradually increasing. The typical star topology in the TTE network system can no longer meet the needs of data interaction. High-speed TTE network has become the focus of research. The real-time and certainty of the time-triggered Ethernet network is based on the high-precision global synchronous clock. Therefore, realizing the clock s...

AI Technical Summary

Problems solved by technology

This method has the following deficiencies: the method of obtaining time stamps at the physical layer requires the use of a dedicated PHY chip that supports the IEEE 1588 protocol, and this method is inseparable from the central processing unit CPU to complete the analysis and calculation functions, resulting in a poor general-purpose synchronization solution. sex and transplantation

The disadvantage of this method is that it is only designed for the time synchronization scheme, and does not consider that other data frames and synchronization frames seize the MAC transmission channel, resulting in the synchronization frame being discarded by the MAC, and the stability of clock synchronization is affected; at the same time, the synchronization frame Frame analysis is performed when sending to the network port. When facing a high-speed network port, there will be a problem that the synchronization frame is sent by the network port before being parsed. The synchronization method is only applicable to low-speed network ports and has poor adaptability

[0006] Through the above analysis, the problems and defects of the existing technology are: the existing IEEE 1588 clock synchronization scheme is not suitable for TTE cascaded networks; it needs a dedicated PHY chip and CPU, which has poor versatility and portability; it is not suitable for high-speed The network does not consider the problem of synchronous frames and other data frames preempting the MAC transmission channel, which has poor stability and adaptability

[0007] The difficulty of solving the above problems and defects is: the two clock models proposed by the IEEE 1588 protocol suitable for switching nodes, the boundary clock and the transparent clock, both have their own defects, and it is necessary to expand a clock model to solve the defects of the boundary clock and the transparent clock , so it is suitable for TTE cascaded networks; in order to improve the symmetry of the synchronization link, the position of the synchronization frame to get the time stamp should be as close as possible to the bottom layer, but there is a problem that a dedicated PHY chip is required to get the time stamp at the physical layer; for For high-speed network ports, it is necessary to ensure that the frame type has been analyzed when the synchronous frame is sent, which is used to correct the timestamp field in time; there are other asynchronous data frames in the network, and it is necessary to consider the problem that the synchronous frame and other data frames occupy the MAC transmission channel

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