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Novel multilayer tunneling junction and application thereof in double-junction laminated battery

A tunneling junction, a new type of technology, applied in circuits, photovoltaic power generation, electrical components, etc., can solve the problems of poor performance of heterojunction batteries, poor performance of transparent conductive films, and reduced battery performance, and achieve high thermal stability. Effect

Inactive Publication Date: 2020-09-25
ZHEJIANG ZHENENG TECHN RES INST +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] 1) Not resistant to high temperature treatment: amorphous silicon is not resistant to high temperature. When the temperature exceeds 250°C, the quality of amorphous silicon film will decrease significantly, and the performance of heterojunction cells will deteriorate
At the same time, the tunnel junction using amorphous silicon can not withstand the treatment of more than 250 ° C, which seriously limits the scope of use of the bottom cell
When the top cell preparation process exceeds 250°C, the bottom cell based on silicon heterojunction, amorphous silicon / transparent conductive film tunnel junction cannot be used
In addition, the transparent conductive film is also not resistant to high temperature
When the temperature exceeds 400 ° C, the performance of some transparent conductive films is significantly deteriorated
[0008] 2) It is easy to generate lateral leakage
When the lateral conductivity of the transparent conductive film is good, the defects of the top battery are easy to form leakage through the transparent conductive film, which significantly reduces the performance of the battery
Therefore, transparent conductive films with high conductivity are not suitable for tunnel junctions.
[0009] 3) Large parasitic absorption: the optical absorption of the amorphous silicon film is large, and the free carrier absorption of the transparent conductive film is also large
[0010] 4) Although the heterojunction solar cell has the characteristics of high efficiency, less preparation steps, and low temperature coefficient, due to the high cost of equipment, the materials used are expensive, and the cost of the cell is high

Method used

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  • Novel multilayer tunneling junction and application thereof in double-junction laminated battery
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  • Novel multilayer tunneling junction and application thereof in double-junction laminated battery

Examples

Experimental program
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Effect test

Embodiment 1

[0045] A silicon oxide layer with a thickness of less than 5nm, that is, the first ultra-thin dielectric layer 2, is prepared on a p-type silicon substrate by wet chemical oxidation, high temperature oxidation or plasma-assisted oxidation, and is prepared on it by PECVD and other thin film deposition equipment A layer of p-type heavily doped silicon film 7 precursor with a thickness of 5-200nm, followed by annealing at a high temperature of 500-1100°C to obtain the first layer of heavily-doped silicon film layer, and then prepare the second layer on top by the same method Ultra-thin dielectric layer 4 and a layer of n-type heavily doped silicon thin film 6 precursors with a thickness of 5-200nm, followed by annealing the second heavily doped silicon thin film layer by rapid annealing (annealing temperature is 600-1000°C) . The prepared tunneling junction based on crystalline silicon bottom cell is as follows figure 2 As shown, the contact resistivity is about 0.01mΩ·cm2, and...

Embodiment 2

[0047] A silicon oxide layer with a thickness of less than 5nm, that is, the first ultra-thin dielectric layer 2, is prepared on the n-type silicon substrate by wet chemical oxidation, high temperature oxidation or plasma-assisted oxidation, and is prepared on it with thin film deposition equipment such as PECVD. A layer of n-type heavily doped silicon thin film 6 precursor with a thickness of 5-200nm, followed by annealing at a high temperature of 500-1100°C to obtain the first heavily doped silicon thin film layer, and then prepare the second layer on top by the same method An ultra-thin dielectric layer 4 and a p-type heavily doped silicon thin film 7 precursor with a thickness of 5-200nm, followed by annealing the second heavily doped silicon thin film layer by rapid annealing (the annealing temperature is 600-1000°C) . The prepared tunneling junction based on crystalline silicon bottom cell is as follows image 3 As shown, the contact resistivity is about 0.01mΩ·cm2, and...

Embodiment 3

[0049] Under certain conditions, the preparation of the tunnel junction structure can also be realized by omitting the second ultra-thin dielectric layer 4: on the p-type silicon substrate, a layer with a thickness of less than The 5nm silicon oxide layer is the first ultra-thin dielectric layer 2, and a p-type heavily doped silicon thin film 7 precursor with a thickness of 5-200nm is prepared on it with a thin film deposition equipment such as PECVD, and then heated at a high temperature of 500-1100°C Perform annealing to obtain the first layer of heavily doped silicon thin film layer, omit the second ultra-thin dielectric layer 4, directly prepare a layer of n-type heavily doped silicon thin film 6 precursor with a thickness of 5-200nm, and then use the method of rapid annealing Annealing the second heavily doped silicon thin film layer (annealing temperature is 600-1000°C). The prepared tunneling junction based on crystalline silicon bottom cell is as follows Figure 4 As ...

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Abstract

The invention relates to a novel multilayer tunneling junction and a double-junction laminated battery thereof. The novel multilayer tunneling junction comprises a crystalline silicon substrate, a first ultra-thin dielectric layer, a first heavily doped silicon film, a second ultra-thin dielectric layer and a second heavily doped silicon film, a second heavily-doped silicon film, a second ultrathin dielectric layer, a first heavily-doped silicon film, a first ultrathin dielectric layer and a crystalline silicon substrate are sequentially arranged in the novel multilayer tunnel junction from top to bottom. The crystalline silicon substrate is n-type crystalline silicon or p-type crystalline silicon. The novel multilayer tunneling junction has the beneficial effect that the structure based on the silicon substrate-dielectric layer-first layer silicon thin film is a crystalline silicon cell technology named as passivation tunneling. The technology has a good silicon wafer surface passivation effect and a good carrier collection effect, full-surface carrier collection can be realized by adopting the passivation contact structure, and a metal electrode is not needed, so that the carrierrecombination rate of the whole silicon wafer surface is very low.

Description

technical field [0001] The invention relates to double-junction solar cells and the field of perovskite / crystalline silicon double-junction cells, and particularly includes a novel multilayer tunnel junction and its application in double-junction laminated cells. Background technique [0002] The existing mainstream solar cell technology - crystalline silicon solar cell has gradually approached the theoretical efficiency. In order to further increase the efficiency of solar cells, new technologies with higher theoretical efficiencies must be developed. Double-junction tandem solar cells can improve the utilization of solar spectrum, reduce thermal electron loss, and have higher theoretical efficiency than single-crystalline silicon solar cells. In recent years, they have gradually attracted widespread attention in the photovoltaic industry. [0003] Specifically, the double-junction cell improves the utilization of the solar spectrum through two sub-cells with different ban...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L31/068H01L31/0236H01L31/18
CPCH01L31/02366H01L31/068H01L31/1804Y02E10/547Y02P70/50
Inventor 寿春晖曾俞衡叶继春闫宝杰郑晶茗卢琳娜廖明墩杨熹盛江
Owner ZHEJIANG ZHENENG TECHN RES INST
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