Security coprocessor structure based on RISC-V instruction extension

Abstract

The invention discloses a security coprocessor structure based on RISC-V instruction extension. The special instruction execution unit and the general instruction execution unit are respectively in control connection with the output result; the security instruction encoding logic given by the processor main pipeline decoding stage performs detailed decoding according to the instruction code and sends the instruction to the special instruction execution unit or the general instruction execution unit; after the instruction is executed, the operation result is output to the write-back stage of the processor main assembly line through the output result control logic, and write-back operation of the general register is achieved through the processor main assembly line. According to the method,the problem of instruction set authorization is avoided, meanwhile, the invasiveness to an original processor is effectively reduced, the application range of encryption and decryption algorithms is expanded, and the method has high application value.

Description

Technical field [0001] The invention belongs to the technical field of integrated circuit design and processor design, and specifically relates to a security coprocessor structure based on RISC-V instruction extension. Background technique [0002] The military application field represented by aerospace applications is facing more and more serious information security threats. Malicious attackers can use a variety of methods to monitor core electronic systems to achieve the purpose of stealing or tampering with key military information. Currently, most of the instructions and data in embedded systems are stored in external SRAM or DRAM, so by adding a small amount of hardware changes to the circuit board, the data on the storage bus can be intercepted, and even the data can be modified in reverse. Based on this practical demand, both the program and data in the off-chip memory need to be encrypted, which requires the processor to decode the program data and re-encode and write th...

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Problems solved by technology

[0004] (1) "Standard instruction + bus IP", this solution is the simplest to implement in hardware, such as "Coprocessor for Encryption and Decryption Process Control" published by Wang Jianfei et al. The standard bus interface can be integrated into the processor system naturally. At the same time, since it does not involve the modification of the instruction set, there is no need to modify the compiler. However, there is a performance bottleneck in this structure, mainly due to the control of IP and the original text / encryption The transmission of files must be controlled by the processor, and each operation must pass through the system bus, and the efficiency is often not as expected;

[0005] (2) "Instruction extension + custom execution unit", this form is to customize and modify the processor from the bottom layer. First, the instruction is extended based on the commercial instruction set, and then the corresponding execution unit is designed at the execution level of the pipeline. From the software point of view, the method involves the authorization of commercial instruction sets, and from the hardware point of view, the substantial modification of the pipeline will cause the adequacy of the verification coverage. Customized design of an encryption algorithm, which is poor in versatility and universality;

[0006] (3) "Instruction extension + coprocessor" also performs instruction extension on the basis of commercial instruction sets, but it does not modify the original processor pipeline structure, but integrates an independent acceleration engine outside the pipeline, because it does not change the mainstream pipeline structure, so the functional complexity is lower, but there are still issues of authorization and universality

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