Method and system for establishing standard cell library, and chip design method and system

Abstract

The invention provides a method and system for establishing a standard cell library, a chip design method and system and a computer storage medium. According to the scheme, the fixed layout mode is designed in advance, and the original unit library is designed according to the fixed layout mode, so that the phenomenon that the design rule is violated due to the process change of the chip to be designed when the obtained standard unit library is applied to chip design is avoided; meanwhile, the circuit characteristics of the standard cell library and the condition of using the standard cell library in the ASIC design process are considered; the consideration process requirements and the requirements of various product application ends are also added; a table look-up mode and a logic synthesis function of a synthesis engine are utilized to adjust the corresponding original units in the original unit library, so that the relatively complete standard unit library which can better meet thechip design requirements of a new process and a new application requirement can be quickly and automatically obtained, meanwhile, the problem that SPICE-level line simulation is slow is solved, and time and labor cost are saved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design automation, in particular to a method and system for establishing a standard cell library, a chip design method and system, and a computer storage medium. Background technique [0002] At present, the semi-custom chip design method based on the standard cell library has been widely used in integrated circuit design, that is, the current layout design of the integrated circuit includes the design based on the standard cell library. The standard cell library is a general term for the unit symbol library, circuit structure library, function description library, layout library, timing power library, physical view library, design rules and interconnection parasitic parameter model library required for integrated circuit design. The design of the standard cell library refers to the design of some standard cells (such as combinational logic, sequential logic, physical cells, etc.) Duri...

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Problems solved by technology

[0004] (1), a method for building a standard cell library from scratch, specifically, the process from the circuit design of each standard cell to the completion of the layout design of the standard cell is performed once, such as the invention patent application CN103559352B proposed The method of establishing standard unit; this method of establishing a standard unit library from scratch has the following defects: due to the large number of types of the standard unit library and the number of standard units included, each new standard unit is established from scratch If so, time-consuming and labor-intensive;

[0005] (2), utilize the circuit characteristics of the standard cell library to speed up the establishment of a new standard cell library. For example, the invention patent application CN105373668B discloses a circuit design method for the standard cell library, which is to form each functional module for logical synthesis, and perform block processing in advance. Combining again, because the number of blocks processed by blocks (corresponding to the number of required standard cell libraries) is less than the original functional modules, it can save a certain amount of time and manpower; but this method has the following defects: Although block processing is done, CN 103559352 B SPICE-level circuit simulation is still required for individual blocks, as well as re-making and fine-tuning of the physical layout, which is still time-consuming and laborious, and cannot meet the needs of fast and efficient chip design;

But this method has the following defects: although the situation of using the standard cell library in the ASIC design process is considered, it does not consider the application requirements of the product, because the application requirements of each chip are often different, so the standard cell library required is also different, such as low The application of power consumption only needs pure CMOS design, and the driving strength is relatively small, while the high-speed application will use the design of dynamic logic, and its driving ability is relatively large. It can be seen that this method does not consider the product Many unnecessary standard units will be generated, which will not only cause waste of resources, but also fail to meet various application requirements and general chip design requirements.

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