Novel chip packaging body and packaging method thereof

Abstract

The invention provides a novel chip packaging body and a packaging method thereof. The novel chip packaging body comprises a base plate, insertion pins and a cap; the base plate comprises a substrate,through holes, a well bottom, golden fingers and a base step; and the through holes are divided into inner-layer through holes and outer-layer through holes. The production process of the novel chippackaging body is simple and flexible, is compatible with existing wire bonding environments, and can be used for rapidly preparing a sample at low cost in an engineering stage. The substrate of the novel chip packaging body is made of specific phenolic plastic, so that the substrate has the characteristics of high hardness, high temperature resistance, wear resistance, corrosion resistance, insulation and the like, and is electrically connected with a chip through combining pins. According to the packaging method of the novel chip packaging body, the cap can be directly and manually added, sothat external force-induced damage is avoided; the design of the method meets FA related requirements in the engineering stage; peripheral devices are conveniently added; and electric damage can be directly observed for failure analysis.

Description

technical field [0001] The invention relates to the technical field of integrated circuit packaging, in particular to a novel chip package and a packaging method thereof. Background technique [0002] Packaging is very important for chips. On the one hand, the chip after reduction needs to be isolated from the outside world to prevent impurities in the air from corroding the chip circuit and causing electrical performance degradation; on the other hand, the packaged chip is also convenient for testing and transportation. . Such as figure 1 As shown, the structure of the existing chip plastic package is shown. The plastic package includes a tube leg 110 and a tube shell 120. The tube leg 110 communicates, and the tube shell 120 can protect the packaging process. There are many forms of packaging, such as DIP, QFP, PGA, BGA, SOP, QFN, etc. In the product engineering stage, most small and medium-scale integrated circuits will adopt dual in-line packaging (DIP packaging) or mo...

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Problems solved by technology

[0003] In view of the deficiencies in the above-mentioned prior art, the purpose of the present invention is to provide a novel chip package and its packaging method, the novel chip package includes a base plate, pins and caps, the novel chip package solves the problem of integration The problem of slow speed and high cost of sample preparation in the circuit engineering stage, while increasing the number of leads, realizes low-cost and fast sample capping in the engineering stage, and meets FA-related requirements such as adding peripheral devices and directly observing electrical damage

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