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A convolution computing accelerator based on 1t1r memory array and its operation method

A memory array, 1T1R technology, applied in the field of digital circuits, can solve problems such as large delay, and achieve the effect of simplifying the calculation process, improving processing efficiency, saving energy consumption and calculation time

Active Publication Date: 2022-02-15
HUAZHONG UNIV OF SCI & TECH
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] Aiming at the defects of the prior art, the purpose of the present invention is to propose a 1T1R memory array-based convolution computing accelerator and its operation method, aiming to solve the problem of delay caused by the separation of storage and computation in the computing architecture in the prior art. big problem

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  • A convolution computing accelerator based on 1t1r memory array and its operation method
  • A convolution computing accelerator based on 1t1r memory array and its operation method
  • A convolution computing accelerator based on 1t1r memory array and its operation method

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Embodiment 1

[0047] Write the number to be convolved in the resistive variable unit, specifically, such as image 3 Figure (a) is a schematic diagram of voltage control for writing data "1" in a memory cell. When data "1" is written in a memory cell, a voltage V greater than the turn-on voltage of the transistor is applied to the gate of the transistor. G , so that the source and drain of the transistor are turned on, and the turn-on voltage of a relatively mature transistor is about 0.7V. In the present invention, the operating voltage V applied to the gate G A voltage greater than 0.7V. In addition, the source of the transistor is grounded (GND), and at the same time, a forward voltage V greater than or equal to the first threshold is applied to the anode of the resistive switching unit. set , and all the selection lines, word lines and bit lines where the cells without data stored in the array are located are suspended. According to the conduction characteristics of the transistor, t...

Embodiment 2

[0056] In the 1T1R array, complete the "AND" operation of multiple resistive variable units in one step, such as the convolution kernel [0 1 1] and the number to be convolved When performing an "AND" operation, such as Figure 5 As shown, first convert the convolution kernel [0 1 1] into a structure of 3 rows and 1 column Convert the number to be convolved into a structure of 3 rows and 2 columns Make the number of rows of the convolution kernel equal to the number of rows of the number to be convoluted, and then write the number to be convoluted into the first three rows and the first two columns of the 1T1R memory array in the form of the resistance state of the resistive unit, and in the first three A voltage V greater than or equal to the absolute value of the second threshold is applied to the word line where the row is located. reset , ground the bit lines where the first two columns are located (GND), and the selection lines, word lines, and bit lines where the res...

Embodiment 3

[0062] The results after the multiplication of the convolution kernel and the number to be convoluted in Embodiment 2 are summed by column, as Figure 6 As shown, a voltage V greater than the turn-on voltage of the transistor is applied to the selection line where the resistive switch unit for storing data is located. G , apply a voltage V less than the first threshold value on the word line where the resistive switch unit storing data is located read , ground the bit line (GND) where the resistive switch unit with data stored is located; and suspend the selection line, word line and bit line where the cells with no data stored in the array are located. Calculate the ratio of the total current on the column where the resistive variable unit is stored in to the reference current as the sum of the calculation results of each column, where the reference current is the read current when the resistive variable unit is in a low-resistance state, that is, the low-resistance state Re...

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Abstract

The invention discloses a convolution calculation accelerator based on a 1T1R memory array and an operation method thereof. The convolution calculation accelerator adopts a 1T1R memory array structure, which solves the problem of leakage current in the array; Input different voltages on the word line, bit line, and selection line of the 1T1R memory array to realize "AND" logic operation and total current reading, and complete the multiplication and addition steps in the convolution calculation, thereby realizing the convolution operation And the calculation process is simplified; the present invention realizes the binary multiplication operation in parallel, and completes the multiplication operation of the convolution kernel for all data in one step, and the operation results can also be read in parallel, which greatly improves the processing efficiency. In addition, the present invention realizes the fusion of storage and computing by adopting 1T1R memory array, greatly saves energy consumption and computing time, and solves the problem of large delay caused by the separation of storage and computing in the computing architecture in the prior art.

Description

technical field [0001] The invention belongs to the field of digital circuits, and more specifically relates to a convolution calculation accelerator based on a 1T1R memory array and an operation method thereof. Background technique [0002] Convolutional neural network is a kind of feed-forward neural network with convolution calculation and deep structure, and it is one of the representative algorithms of deep learning. With the introduction of deep learning theory and the improvement of numerical computing equipment, convolutional neural networks have developed rapidly and have been widely used in computer vision, natural language processing and other fields. The convolutional neural network structure includes an input layer, a hidden layer, and an output layer, and the hidden layer includes a convolutional layer, a pooling layer, and a fully connected layer. Compared with the general fully connected neural network, the sparse connection in the convolutional neural netwo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06N3/04G06N3/063
CPCG06N3/063G06N3/045
Inventor 李祎程龙缪向水
Owner HUAZHONG UNIV OF SCI & TECH
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