Logic Expression Extraction and Switch Level Design Method for CMOS Transmission Gate Logic Circuit

Abstract

The invention discloses a logical expression extraction and switch-level design method of a CMOS transmission gate logic circuit, which expands the Boolean algebra system to obtain the extended Boolean algebra system; the corresponding switch-level signal flow diagram is established by the CMOS transmission gate logic circuit From this model, the equivalent signal flow graph model of the output function of the circuit is extracted, and the switch-level function expression of the circuit is obtained by combining the switch-level signal flow graph model with the extended Boolean algebra system, thereby obtaining the CMOS transmission gate logic circuit . The CMOS transmission gate logic circuit designed by the method of the present invention requires less MOS tubes and fewer connections, which can reduce power consumption and save chip area; and the designed switching level CMOS transmission gate logic circuit It is full-swing and suitable for the design of low-power CMOS circuits.

Description

technical field [0001] The invention relates to a logic expression extraction and switch level design method of a logic circuit, in particular to a logic expression extraction and switch level design method of a CMOS transmission gate logic circuit. Background technique [0002] Complementary metal-oxide semiconductor (CMOS) integrated circuits are widely used in very large-scale integrated circuits (VLSI) because of their low power consumption, high integration, strong anti-interference ability, and wide power supply voltage range. Among them, logic circuits composed of various combinations of CMOS transmission gates have become a wider circuit form. Studies have shown that a simpler circuit structure can often be obtained by using the switch-level design method. This circuit structure is a CMOS transmission gate logic circuit composed of various combinations of CMOS transmission gates. [0003] However, how to extract the corresponding logic functions from the actual or d...

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Problems solved by technology

[0016] (2) The power supply voltage of the circuit is reduced, which reduces the dynamic power consumption; but the process feature size is reduced, so that the threshold voltage of the MOS transistor and the thickness of the gate oxide layer are correspondingly reduced, and the subthreshold value generated by the subthreshold (weak inversion) conduction of the MOS transistor The static power consumption of the MOS tube caused by leakage current and gate leakage current increases, and the reduction of power consumption should consider reducing dynamic power consumption and reducing static power consumption

It can be seen that there is a contradiction between saving area, reducing power consumption and increasing speed

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