High-low temperature aging test box for semiconductor memory

Abstract

The invention belongs to the technical field of high-low temperature aging test of semiconductor memory, and discloses a high-low temperature aging test box of semiconductor memory, which is providedwith a normal temperature region and one or more groups of test regions composed of a first temperature region, a second temperature region and an isolation region. The temperature difference betweenthe two temperature zones is constant; the normal temperature area is used for placing the upper computer and the switch, and the heat dissipation device is arranged for the upper computer and the switch; a test area is used for place semiconductor memory aging test equipment; a first temperature zone for placing a first backplane of the aging test system and a test core board removably pluggableon the first backplane; a second temperature region for placing a second backplane and a test board removably insertable on the second backplane; the isolation area is provided with a through board, and the test signal and the power signal sent from the test core board located in the first temperature area are transmitted to the test board located in the second temperature area through the throughboard. A heat sink for dissipating heat to the through plate is provided on the side of the isolation zone to reduce the influence of the temperature of the second temperature zone on the first temperature zone.

Description

Technical field [0001] The invention belongs to the technical field of semiconductor aging testing, and more specifically relates to a high and low temperature aging test box for semiconductor memory. Background technique [0002] Semiconductor memory has a certain failure probability. The relationship between the failure probability and the number of uses conforms to the characteristics of the bathtub curve. The failure probability of the memory is high when it is used. After a certain number of uses, the failure probability is greatly reduced until it is close to or reaches its use. After the lifetime, the failure probability of the memory will increase again. So far, no memory manufacturer has dared to ignore the failure problem of semiconductor memory. Generally, aging test (Test During burn-in, TDBI) is used to accelerate the occurrence of memory failure probability and directly enter the product stability period to solve the problem. [0003] The overall plan of semiconducto...

AI Technical Summary

Problems solved by technology

However, the performance of the test board placed in the high-temperature aging device will be greatly affected by the temperature, and no low-temperature test plan is given; moreover, this test plan is a general test method for conventional integrated circuits, not a test specifically for semiconductor memory method

[0005] The Chinese patent with the publication number CN1482660A discloses the test burner system, discloses the internal and external layout of the burner room (aging room) in the test burner system, and the burner board placed in the burner room and the extension placed outside the furnace. Circuit board; its advantage is that the high and low temperature test and the normal temperature test can be carried out simultaneously without mutual influence, which saves test time and cost; but the patent document does not disclose the specific performance, function, structure and layout of the burn-in board and the extended circuit board; Moreover, the performance of the burner board will be greatly affected by the high and low temperature of the test burner system

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