Manufacturing method of grid

Abstract

The invention discloses a method for manufacturing a gate, which comprises the steps of: forming a gate dielectric layer and a polysilicon gate; forming a hard mask layer in which a first nitride layer and a second oxide layer are stacked; photoetching and etching to form a gate; Form a nitride layer sidewall on the side of the gate; form a nitride layer contact hole etching stop layer; form an oxide layer interlayer film; use the contact hole etching stop layer as a stop layer to perform the first chemical mechanical polishing of the oxide layer Carry out etching of the nitride layer to remove the nitride layer on the top of the second oxide layer of each gate; perform etching of the oxide layer to remove the second oxide layer on the top of the gate, and the thickness of the interlayer film is reduced synchronously; The polysilicon gate is used as a stop layer for a second chemical mechanical polishing of the remaining nitride and oxide layers above the top surface of the polysilicon gate. The invention can stably control the height of the grid and improve the consistency of the height of the grid, does not need a photomask, and has low cost.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a grid. Background technique [0002] In the existing advanced logic chip technology, components usually include n-type field effect transistors (FETs) or nFETs and p-type field effect transistors or pFETs. In order to increase the electrical performance of components, an additional component enhancement process is performed in addition to the pFET or nFET process. These component enhancement processes will directly affect the gate heights of various subsequent components, resulting in differences in the gate heights between different subsequent components and affecting the electrical properties of the components. Such as figure 1 As shown, it is a structural diagram of a gate formed by a conventional gate manufacturing method; a field oxide layer 102 is formed on a semiconductor substrate such as a silicon substrate 101,...

AI Technical Summary

Problems solved by technology

In the process of etching back the oxide layer 105, the photoresist 206 has a certain loss. When the oxide layer 105 on the top of some gates has not been removed, the height of part of the photoresist 206 is already lower than the height of the polysilicon gate 103. , thus exposing the sides of the polysilicon gate 103

The transition loss of the photoresist 206 caused by the excessive height difference of the gate is likely to cause damage to the active region and the polysilicon gate, which will affect the electrical properties of the original.

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