JFET

Abstract

The invention discloses a junction field effect transistor, which comprises an N-type deep well, wherein a drift region field oxide is formed in a surface area of the N-type deep well; a P-type top layer is formed on the surface of the N-type deep well at the bottom of the drift region field oxide and comprises a first top layer and a second top layer; the first top layer is taken as a gate regionof the JFET; the N-type deep well covered with the gate region of the JFET is taken as a channel region of the JFET; and the first top layer also extends into a semiconductor substrate at the outer side of the N-type deep well along the width direction of the channel region of the JFET, a contact hole is formed in the top of the extended part and the first top layer is connected with a gate of the JFET. According to the junction field effect transistor, the pinch-off voltage of a device can be increased and the gate leakage current of the JFET can be reduced; and the junction field effect transistor can be integrated with an LDMOS, so that the process cost is low.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a junction field effect transistor (JFET). Background technique [0002] JFET uses the PN junction as the gate of the device to control the opening and closing of the channel. When the PN junction is negatively biased on the gate, both sides of the PN junction are depleted. When the channel is completely depleted, the device is in the pinch-off state of the channel. due. Otherwise, the device turns on. [0003] The ultra-high voltage junction field effect transistor needs the drain to withstand high voltage. Usually, the N-type deep well of the high-voltage LDMOS is used as the N-type deep well of the JFET to withstand high voltage, and the channel of the high-voltage LDMOS is used as the gate of the JFET, so that ultra-high voltage can be produced. JFET can also share the photolithography plate with high-voltage LDMOS, saving process costs. [0004] Such as figure 1 Show...

AI Technical Summary

Problems solved by technology

[0009] At the same time, in the existing JFET structure, as the drain terminal voltage rises, the leakage current at the gate terminal of the JFET will increase sharply, and eventually the JFET will be turned on and burned.

[0010] And because the JFET vertical channel is formed by the fixed process of the P-type well region 104 and the N-type deep well 102, that is, when the structure of the LDMOS is real, the process of the P-type well region 104 and the N-type deep well 102 It will be fixed, which makes the structure of the channel region of the JFET unadjustable, so it is difficult to achieve a higher pinch-off voltage, so that it cannot meet the customer's special design needs for the pinch-off voltage

Images