Vertical double diffused field effect transistor and its manufacturing method

Abstract

A vertical double diffusion field effect transistor comprises an N type substrate, first layers of N type extension, first grooves, second grooves, P type extension, second layers of P type extension,third grooves, second layers of P type extension, first N type injection areas, second N type injection areas, first P type injection areas, second P type injection areas, silicon oxide layers, polycrystalline silicon layers, medium layers, first through holes and second through holes, wherein the first grooves and the second grooves are formed in the surfaces of the first layers of N type extension, the P type extension is formed in the first grooves and the second grooves, the second layers of P type extension are formed on the first layers of N type extension and the P type extension, thethird grooves penetrate through the second layers of P type extension, the second layers of P type extension are located in the third grooves, the first N type injection areas and the second N type injection areas are located on the surfaces of the second layers of P type extension and correspond to the first grooves and the second grooves, the first P type injection areas and the second P type injection areas penetrate through the first N type injection areas and the second N type injection areas and extend to the second layers of P type extension, the silicon oxide layers and the polycrystalline silicon layers are formed sequentially, the medium layers are formed on the polycrystalline silicon layers, the first N type injection areas, the second N type injection areas and third injectionareas, the first through holes penetrate through the medium layers and correspond to the first N type injection areas and the first P type injection areas, and the second through holes penetrate through the medium layers and correspond to the second N type injection areas and the second P type injection areas.

Description

【Technical field】 [0001] The invention relates to the technical field of semiconductor chip fabrication, in particular to a vertical double diffused field effect transistor (VDMOS) and a fabrication method thereof. 【Background technique】 [0002] The drain and source poles of the vertical double diffused field effect transistor (VDMOS) are respectively on both sides of the device, so that the current flows vertically inside the device, increasing the current density, improving the rated current, and the on-resistance per unit area is also small, which is a A very versatile power device. The most important performance parameter of a vertical double diffused field effect transistor (VDMOS) is the operating loss, which can be divided into three parts: conduction loss, cut-off loss and switching loss. The conduction loss is determined by the conduction resistance, the cut-off loss is affected by the reverse leakage current, and the switching loss refers to the loss caused by th...

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Problems solved by technology

However, N-type implantation is a full-chip implantation, and non-JFET regions will also be implanted, which will affect device performance.

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