Digital phase-locked loop frequency synthesis device

Abstract

The invention discloses a digital phase-locked loop frequency synthesis device. The device comprises an orthogonal voltage-controlled oscillator, an output buffer, an eight-division frequency-divider,a phase interpolator, a digital processor, a digital time converter, a sampler, an analog-to-digital converter, a digital loop filter, a digital-to-analog converter and a frequency locking module. The digital phase-locked loop frequency synthesis device disclosed by the invention can generate 28-32 GHz continuous coverage millimetre-wave orthogonal signal output, and can satisfy the local oscillation requirement of a transceiver in the frequency band; furthermore, voltage signals are converted into digital signals through the analog-to-digital converter; the equivalent time resolution is improved; the in-band phase noise of output signals is improved; the required delay coverage range of the digital time converter is reduced; the linearity of the digital time converter is improved; and the spurious performance of output signals is improved.

Description

technical field [0001] The invention belongs to the technical field of frequency synthesis of communication and on-chip systems, and in particular relates to a digital phase-locked loop frequency synthesis device. Background technique [0002] The frequency synthesis device is a frequency synthesis module with low noise, low jitter and high precision. In the field of communication, it provides a local oscillator signal for the transceiver, and its performance greatly affects the performance level of the entire system. [0003] In recent years, with the development of the Internet of Things, the rise of new applications such as ultra-high-resolution video and virtual reality, the amount of data that needs to be transmitted has greatly increased. Traditional wireless communication standards such as 2G, 3G, and 4G are limited by carrier rate and transmission bandwidth, and their data transmission rate has been increasingly unable to meet the requirements. In order to meet the...

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Problems solved by technology

[0004] In addition, as the process node of integrated circuits decreases, the performance of gain and subthreshold leakage, which are critical to the performance of analog circuits, becomes worse. Therefore, the traditional analog charge pump phase-locked loop has become increasingly unsuitable for advanced Process Node Design Requirements

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