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Circuit verification

A circuit and sub-circuit technology, applied in the field of circuit verification, to achieve the effect of improving efficiency

Inactive Publication Date: 2017-08-01
EASY LOGIC TECH LTD
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  • Abstract
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Problems solved by technology

Therefore, traditional formal verification methods can only be used for smaller circuits

Method used

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Embodiment Construction

[0026] Exemplary embodiments relate to algorithms or devices that improve arithmetic circuit verification.

[0027] Circuit verification is a very necessary step in IC design and manufacturing. The verification process takes about 60% or more of the entire design cycle. Modern integrated circuits often contain millions of tiny circuit elements, such as circuit gates or transistors, so verification cannot be accomplished manually with paper and pen. Therefore, verification is usually accomplished with the aid of computer hardware and corresponding electronic design automation (EDA) software tools.

[0028] The effectiveness and efficiency of circuit verification has a great impact on the chip industry. Undetected errors make the entire chip worthless. Inefficient verification (such as too long run time or too high complexity) can lengthen the overall design cycle, thereby delaying the time to market to the detriment of benefits. In addition, too low efficiency or too high o...

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Abstract

Provided is a totally new formal verification algorithm aiming at an arithmetic circuit. One example embodiment provides a new formal method which couples (combines) a satisfiability (SAT) solver and a unique Reverse Engineering (RE) method which makes use the arithmetic logical circuit structure properties (e.g. 1-bit adder structure, Carry tree structure) to achieve the algorithm for arithmetic circuits regardless of its size. The example embodiment provides basic through of how to optimize the operational complexity of a conventional arithmetic circuit verification method. The basic through is shown as followed: assuming that there are two arithmetic circuits f and g; conducting equivalence checking of the two arithmetic circuits by firstly generating a conjunctive normal form (CNF) encoding; and determining whether the encoding of the two arithmetic circuits is equal through a satisfiability (SAT) tool. If the structural difference between f and g is minimized as far as possible before generating a conjunctive normal form (CNF) encoding, the arithmetic circuit verification is completed in polynomial time rather than in exponential time.

Description

[0001] Claiming the benefit of the earlier application [0002] This application claims the benefit of US Provisional Patent Application 62 / 281,735, filed January 22, 2016, entitled "Tai-Chi Coupling Optimization Method: Coupling Reverse Engineering and SAT to Tackle NP-Complete Arithmetic Circuitry Verification," the contents of which are hereby incorporated by reference in their entirety Incorporated herein. technical field [0003] In general terms, the present invention relates to algorithms and apparatus for circuit operations. Background technique [0004] The complexity of integrated circuits (ICs), such as arithmetic circuits, has grown significantly over the past few decades. In a standard circuit design process, more than 60% of the time is often spent on verification. Because integrated circuits often contain millions of tiny circuit elements, such as circuit gates or transistors, verification cannot be done manually by humans. Therefore, verification is usuall...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/3323G06F30/398G06F30/33
Inventor 刁屹魏星吴有亮
Owner EASY LOGIC TECH LTD
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