Multi-loop self-biasing phase-locked loop circuit and clock generator

Abstract

The invention is applicable to the field of integrated circuits, and provides a multi-loop self-biasing phase-locked loop circuit and a clock generator. The circuit comprises a multi-phase output phase frequency detector, a reverse unit, a first charge pump, a second charge pump, a third charge pump, a switch unit, a voltage-controlled oscillator array and a frequency divider, wherein when a frequency difference between a signal output by the frequency divider and input reference frequency is less than a first threshold, the first and second charge pumps work simultaneously, the output current of the first charge pump is used for controlling a voltage-controlled oscillator to work so as to achieve output with a wide frequency range; the second charge pump and the third charge pump forms a control voltage on a second energy storage unit to control the current of the switch unit, so as to achieve dynamic adjustment of a ratio between the current of the chare pump and the current of the voltage-controlled oscillator. The multi-loop self-biasing phase-locked loop circuit provided by the invention has the advantages of being wide in application range, good in transportability, wide in input and output range and free from being affect by PVT, and having extremely strong capacity of resistant to technology, supply voltage and ambient temperature.

Description

technical field [0001] The invention belongs to the field of integrated circuits, in particular to a multi-loop self-bias phase-locked loop circuit and a clock generator. Background technique [0002] Due to the advantages of flexible frequency adjustment and small output signal jitter, phase-locked loops have become an indispensable part of modern integrated circuits. For different applications, the requirements for the performance parameters of the PLL are also different, such as: input and output frequency range, frequency division range, output signal jitter / phase noise, power consumption and area, etc. [0003] However, in the current traditional PLL structure, the parameters of each module are basically fixed, and can only output high-performance frequency signals within a narrow working range, such as a very narrow input and output frequency range and frequency division range. However, expanding the range usually leads to output signal jitter and affects product perf...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the embodiment of the present invention is to provide a multi-loop self-biased phase-locked loop circuit, aiming to solve the problem that the existing phase-locked loop cannot The working state dynamically adjusts the parameters of each module to output high-performance frequency signals within the entire working range, resulting in the problem that it cannot be applied to multiple application systems

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