DPWM module for synchronous segmentation delay chain based on FPGA

Abstract

The invention discloses a DPWM module for a synchronous segmentation delay chain based on an FPGA. The DPWM module is characterized by comprising a clock control module, a coarse delay module, a fine delay module, an AND gate and an RS latch, wherein the clock control module is based on a counter; the coarse delay module is based on a phase-locked loop; and the fine delay module is based on an adder chain. According to the DPWM module for the synchronous segmentation delay chain based on the FPGA disclosed by the invention, the temporal resolution, the duty ratio linearity and the stability of a pulse width modulator are improved, and the robustness of the pulse width modulator is reinforced; and thus, the ripples and the stabilization time of a DC-DC converter are shortened, and the overshoot and the ringing occurred in a modulation process are suppressed and are weakened.

Description

technical field [0001] The invention relates to the field of FPGA and power management chips, in particular to a DPWM module based on FPGA-based synchronous segment delay chain. Background technique [0002] The feedback loop of the DC-DC converter is dominated by analog control technology, which has been used for a long time. However, the traditional analog pulse width modulation (APWM) is susceptible to PVT and has poor stability, which makes it impossible for analog control pulse width modulation to achieve higher resolution. With the development of semiconductor technology, traditional analog pulse width modulation (APWM) gradually transitions to digital control pulse width modulation (DPWM), but digital control also has certain shortcomings, the two most important of which are sampling delay and affected Therefore, DPWM needs to have high enough linearity, stability and resolution to ensure the required voltage regulation accuracy and avoid undesired limit loops. How ...

AI Technical Summary

Problems solved by technology

However, traditional analog pulse width modulation (APWM) is susceptible to PVT and has poor stability, making it impossible for analog control pulse width modulation to achieve higher resolution

With the development of semiconductor technology, traditional analog pulse width modulation (APWM) gradually transitions to digital control pulse width modulation (DPWM), but digital control also has certain shortcomings, the two most important of which are sampling delay and affected limited resolution, so DPWM needs to have high enough linearity, stability, and resolution to ensure the required voltage regulation accuracy and avoid undesired limit cycles

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