Method for improving profile of side wall of grid electrode, and semiconductor device manufacturing method

Abstract

The invention provides a method for improving the profile of a side wall of a grid electrode, and a semiconductor device manufacturing method. The method for improving the profile of the side wall of the grid electrode comprises the steps: covering the surface of a formed side wall layer with a protection layer, wherein the protection layer covers the side wall layer, thereby enabling the surface of a semiconductor substrate to tend to be flat; carrying out the vertical etching of the protection layer through employing the punchthrough etching technology with the high etching selection ratio of the side wall layer and the protection layer, so as to remove a part, located on a top plane of a grid structure, of the protection layer, and keep the parts located on side walls and an inclined shoulder of the grid structure; enabling the protection layer on the inclined shoulder to be able to protect the side wall layer below the protection layer in a process of forming the side wall through the partial etching of the side wall layer, thereby reducing the etching loss of a side wall material on the inclined shoulder, and finally obtaining the side wall with the width uniformity. The side wall can increase the effective distance between a contact hole, sequentially formed in a source / drain region, and the grid structure, improves the effect of ion injection of the source / drain regions, solves problems of threshold voltage and leaked current of a device, and improves the performance of the device.

Description

Technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for improving the shape of a gate sidewall and a method for manufacturing a semiconductor device. Background technique [0002] Please refer to figure 1 After the semiconductor manufacturing process enters the nanometer level, spacers 12 are generally used in CMOS devices. The spacers 12 surround the gate 11, which can protect the polysilicon gate and define the source and drain ion implantation of the semiconductor substrate 10. To prevent bridging caused by self-aligned silicide, and to prevent high-intensity and large-dose source / drain implantation 14 from being too close to the channel to cause source / drain punchthrough. [0003] The method of forming the sidewall structure 12 in the prior art usually includes, after the gate 11 is formed, a layer of sidewall material is deposited on the surface of the gate 11 and the semiconductor substrate, and then the semicond...

AI Technical Summary

Problems solved by technology

The sloping shoulder at the top of the existing side wall structure 12 is relatively sharp, which is likely to cause some defects:

[0004] 1. When a large dose of source / drain region implantation 14 is performed on the semiconductor substrate 10 with the sidewall structure 12 as a mask, the implanted ions will easily pass through the sidewall structure 12 and penetrate into the gate, resulting in a threshold voltage Vt of the device and leakage current increase significantly, seriously affecting the quality of the device;

[0005] 2. When the contact hole (CT) 13 is made on the source / drain region of the semiconductor substrate 10, it is easy to generate a stack shift (overlayshift). If both the minimum horizontal distance D1 and the maximum horizontal distance D2 between the gates are reduced, the spacer structure 12 can no longer completely insulate the gate and the contact hole 13, and it is very likely to cause a gap between the gate and the contact hole 13. leakage phenomenon, and eventually degrade the performance of the device

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