Method of forming semiconductor structure

Abstract

The invention provides a method of forming a semiconductor structure. The method comprises the steps of providing a semiconductor substrate with a transistor forming on the surface thereof; forming a first interlayer dielectric layer covering the semiconductor substrate and the transistor; forming a plug in the first interlayer dielectric layer; forming a sacrificial layer covering the first interlayer dielectric layer and the plug; etching the sacrificial layer, and forming a first trench in the sacrificial layer; forming a second interlayer dielectric layer filled in the first trench; removing the remaining sacrificial layer, and forming a second trench which exposes the surface of the plug; and forming a wiring layer filled in the second trench, the bottom of the wiring layer being electrically connected with the plug and the top of the wiring layer having a size smaller or equal to that of the bottom. The effective contact area between the wiring layer and the plug is increased, the resistance drift phenomenon of a metal interconnect structure is improved, damage to the interlayer dielectric layers from the etching process is avoided, the parasitic capacitance is reduced, and the device electrical performance is optimized.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the increasing development of semiconductor integrated circuits, the circuit density inside the semiconductor integrated circuit is increasing, and the number of components contained is also increasing. In semiconductor integrated circuits, metal oxide semiconductor (MetalOxideSemiconductor, MOS) transistors are one of the most important components. With the increasing performance requirements of semiconductor devices in the market, the size of semiconductor devices is becoming smaller and smaller. The manufacturing process of devices has brought many improvements and challenges, and small process deviations will lead to changes in the electrical properties of semiconductor devices. [0003] As an integral part of semiconductor devices, the metal interconnection structure includes wiring...

AI Technical Summary

Problems solved by technology

Before the feature size of the metal interconnection structure is reduced, the current process technology has no obvious adverse effects on the metal interconnection structure, but the continuous reduction of the feature size has brought great challenges to the process technology, and the resistance value of the metal interconnection structure is prone to drift And the problem of increased parasitic capacitance of metal interconnection structure, these problems will reduce the electrical performance of semiconductor devices

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