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A kind of manufacturing method of 100v schottky diode mesa

A technology of Schottky diode and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor device, electrical components and other directions, can solve the problems of forward voltage drop, low junction temperature, large forward voltage drop, etc., to reduce leakage Effects of current and forward voltage drop, increasing metal area, reducing forward voltage drop

Active Publication Date: 2019-01-18
TIANSHUI TIANGUANG SEMICON
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the leakage current increases, the junction temperature of the product decreases, and the device is prone to damage
[0004] (2) Schottky diodes mostly use Ni, Ti, and Pt as metal barriers. Ni and Ti have lower barrier heights, lower forward voltage drop, and lower junction temperature; when the working environment temperature is high, Devices prone to premature failure
Pt barrier junction temperature is higher, but the forward voltage drop is too large

Method used

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  • A kind of manufacturing method of 100v schottky diode mesa

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Experimental program
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Effect test

Embodiment 1

[0030] A method for manufacturing a 100V Schottky diode mesa, comprising the following steps:

[0031] (1) Use cleaning solution I and cleaning solution II in sequence to clean the substrate silicon wafer at a temperature of 70°C, and dry it for later use. The cleaning solution I is made of NH 3 h 2 O, H 2 o 2 and H 2 O is mixed according to the volume ratio of 1:1:5, and the cleaning solution II is composed of HCL, H 2 o 2 and H 2 O is mixed according to the volume ratio of 1:1:5;

[0032] (2) Perform initial oxidation on the cleaned substrate silicon wafer, and the thickness of the oxide layer is 6800Å;

[0033] (3) Perform base photolithography on the front side of the oxidized substrate silicon wafer, implant boron on the P+ ring of the substrate silicon wafer, and then perform annealing treatment;

[0034] (4) Conduct lead hole photolithography on the annealed substrate silicon wafer;

[0035] (5) Carry out mesa lithography on the mesa of the barrier area of ​​th...

Embodiment 2

[0043] A method for manufacturing a 100V Schottky diode mesa, comprising the following steps:

[0044] (1) Use cleaning solution I and cleaning solution II in sequence to clean the substrate silicon wafer at a temperature of 75 ° C, and dry it for later use. The cleaning solution I is made of NH 3 h 2 O, H 2 o 2 and H 2 O is mixed according to the volume ratio of 1:1:5, and the cleaning solution II is composed of HCL, H 2 o 2 and H 2 O is mixed according to the volume ratio of 1:1:5;

[0045](2) Perform initial oxidation on the cleaned substrate silicon wafer, and the thickness of the oxide layer is 7000Å;

[0046] (3) Perform base photolithography on the front side of the oxidized substrate silicon wafer, implant boron on the P+ ring of the substrate silicon wafer, and then perform annealing treatment;

[0047] (4) Conduct lead hole photolithography on the annealed substrate silicon wafer;

[0048] (5) Carry out mesa lithography on the mesa of the barrier area of ​​t...

Embodiment 3

[0056] A method for manufacturing a 100V Schottky diode mesa, comprising the following steps:

[0057] (1) Use cleaning solution I and cleaning solution II in sequence to clean the substrate silicon wafer at a temperature of 80°C, and dry it for later use. The cleaning solution I is made of NH 3 h 2 O, H 2 o 2 and H 2 O is mixed according to the volume ratio of 1:1:5, and the cleaning solution II is composed of HCL, H 2 o 2 and H 2 O is mixed according to the volume ratio of 1:1:5;

[0058] (2) Perform initial oxidation on the cleaned substrate silicon wafer, and the thickness of the oxide layer is 7200Å;

[0059] (3) Perform base photolithography on the front side of the oxidized substrate silicon wafer, implant boron on the P+ ring of the substrate silicon wafer, and then perform annealing treatment;

[0060] (4) Conduct lead hole photolithography on the annealed substrate silicon wafer;

[0061] (5) Carry out mesa lithography on the mesa of the barrier area of ​​th...

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Abstract

The invention belongs to the technical field of an electronic component, and relates to a 100V Schottky diode table-board manufacturing method. On the basis that the product dimension is not increased, a groove is formed through table-board corrosion for a barrier region, and then the objects of increasement of a Schottky barrier metal area and reduction of a positive voltage drop are achieved; HNO<3> in a silicon corrosive solution plays a role in oxidation for silicon, HF plays a role in corrosion for the silicon, HAC plays a role in buffer for a corrosive process in the whole corrosive process, and then the surface of the whole silicon process groove is uniform and smooth; a Ni-Pt60 alloy target material is sputtered on a substrate silicon wafer barrier region to form a stable Ni-Pt60 alloy coating; and different characteristics of metal Ni and metal Pt are used, so a leak current and the positive voltage drop are reduced, and product junction temperature is improved.

Description

technical field [0001] The invention belongs to the technical field of electronic components and relates to a method for manufacturing a 100V Schottky diode mesa. Background technique [0002] Existing 100V Schottky diodes have the following drawbacks: [0003] (1) Schottky diodes need to reduce the forward voltage drop. The main factor affecting the forward voltage drop is the barrier area of ​​the product. The larger the barrier area, the smaller the forward voltage drop. Only by increasing the product area can the barrier area be increased , Reduce the forward voltage drop, and the side effect of the increase in product area will be the increase in leakage current. As the leakage current increases, the junction temperature of the product decreases, and the device is prone to damage. [0004] (2) Schottky diodes mostly use Ni, Ti, and Pt as metal barriers. Ni and Ti have lower barrier heights, lower forward voltage drop, and lower junction temperature; when the working e...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/329H01L29/47H01L29/872
CPCH01L29/47H01L29/66143H01L29/872
Inventor 张志向杜林德
Owner TIANSHUI TIANGUANG SEMICON
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