Analytical method for total dose effect sensitivity of logic gate circuits and cmos digital circuits

Abstract

The invention relates to a method for analyzing the sensitivity of the total dose effect of a logic gate circuit and a CMOS digital circuit, comprising 1) enumerating the working state of the logic gate circuit to be analyzed during the irradiation process, enumerating the state of the logic gate circuit to be analyzed during the test process Working state, the working states in the two processes are arranged and combined to form multiple sets of input signal combinations, 2) The specific structure of the pMOS transistor combination and the specific structure of the nMOS transistor combination that make up the analysis logic gate circuit are simplified and equivalent to inverse 3) Calculate the conductance of each inverter, the combination of the smallest equivalent pMOS conductance and the largest equivalent nMOS conductance will correspond to the strongest total dose sensitivity. The method of the present invention can quickly identify the sensitive nodes of the total dose effect in the circuit, realizes the identification of the sensitive nodes of the total dose effect in the circuit in the design stage, and can be used to guide the reinforcement design, greatly saving the layout area.

Description

technical field [0001] The invention belongs to the research field of total dose effect of CMOS digital integrated circuits. Background technique [0002] Semiconductor device circuits working in the space radiation environment for a long time will be affected by the total dose effect, which is specifically characterized by the degradation of the electrical performance of the device or circuit or even functional failure. [0003] Common methods for total dose hardening of circuits can be divided into three categories: layout hardening, design hardening, and shield hardening. Layout reinforcement refers to the adjustment of the most basic unit, such as changing the ion implantation in the process flow, changing the position or number of well contacts, changing the layout structure of a single tube, etc., see patent application number 201010548221.4, "An anti-total dose radiation hardened transistor structure", etc. Design hardening refers to adjustments at the netlist level...

AI Technical Summary

Problems solved by technology

[0005] Aiming at the lack of existing methods for identifying sensitive areas of CMOS circuits, the existing reinforcement methods do not perform the identification of sensitive areas before the total dose of the circuit is strengthened, resulting in the increase of layout area and the reduction of indicators such as integration, the present invention provides a The analysis method for the sensitivity of the total dose effect of logic gate circuits and CMOS digital circuits can identify the sensitive nodes of the total dose effect, which can be used to guide the reinforcement design and obtain the balance between cost and radiation resistance performance

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