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Photoresist pattern formation method, transistor gate formation method

A technology of photoresist and photoresist layer, which is applied in the formation of photoresist patterns and the formation of transistor gates, and can solve the problems of reducing the low-frequency line width roughness of photoresist patterns

Active Publication Date: 2017-12-29
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The problem to be solved by the present invention is: it is impossible to effectively reduce the low-frequency line width roughness of the photoresist pattern while maintaining the basic shape of the photoresist pattern

Method used

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  • Photoresist pattern formation method, transistor gate formation method
  • Photoresist pattern formation method, transistor gate formation method
  • Photoresist pattern formation method, transistor gate formation method

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0031] like figure 1 As shown, a substrate 100 is provided.

[0032] The substrate 100 may be a commonly used substrate such as a silicon substrate, a silicon germanium substrate, a gallium arsenic substrate, and the like.

[0033] Continue to refer to figure 1 A gate material layer 102 is formed on a substrate 100 as shown

[0034] In this embodiment, the material of the gate material layer 102 is polysilicon, and the formation method of the gate material layer 102 is chemical vapor deposition.

[0035] Continue to refer to figure 1 As shown, a photoresist pattern 104 is formed on the gate material layer 102 .

[0036] The photoresist pattern 104 is used to define the transistor gate. The method for forming the photoresist pattern 104 includes: forming a photoresist layer on the gate material layer 102 ; and patterning the photoresist layer to form the photoresist pattern 104 .

[0037] In this embodiment, the photoresist pattern 104 is basically a cuboid.

[0038] ...

no. 2 example

[0058] The difference between the second embodiment and the first embodiment is that in the second embodiment, as Figure 4 As shown, there are also formed between the photoresist pattern 104 and the gate material layer 102: a hard mask layer 108 above the gate material layer 102, an amorphous carbon layer (amorphous carbon) above the hard mask layer 108 110 , a dielectric antireflection layer (Darc) 112 on the amorphous carbon layer 110 , and a bottom antireflection layer (Barc) 114 on the dielectric antireflection layer 112 .

[0059] On the basis of the first embodiment, the technical solution of the second embodiment can bring the following further beneficial effects: by sequentially setting a hard mask layer between the photoresist pattern and the gate material layer, the amorphous The carbon layer, the dielectric antireflection layer and the bottom antireflection layer can reduce the thickness of the photoresist pattern.

[0060] In this embodiment, the method for formi...

no. 3 example

[0068] The difference between the third embodiment and the first embodiment is that in the third embodiment, the H 2 The gases also include: CH 2 f 2 、CH 3 One or more of F.

[0069] On the basis of the first embodiment, the technical solution of the third embodiment can bring the following further beneficial effects: 2 f 2 、CH 3 Under the action of F, a layer of polymer layer will be formed on the surface of the photoresist pattern, which can prevent the photoresist pattern from reflowing and prevent the photoresist pattern from being unable to flow due to the large degree of reflow. Keep the basic shape.

[0070] In this example, the H 2 The gas also includes CH 2 f 2 and CH 3 F, the process parameters of the first plasma treatment include: the pressure is 2 to 100mtorr, the power of the first radio frequency power supply is 10 to 1000W, the first bias voltage is 0 to 500V (inclusive), H 2 The flow rate is 10 to 500sccm, CH 2 f 2 and CH 3 The flow rate of F is ...

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Abstract

The invention discloses a formation method of a photosensitive resist pattern, and a formation method of a transistor grid. The formation method of the photosensitive resist pattern comprises the following steps: forming a photosensitive resist layer on a substrate; patterning the photosensitive resist layer to form the photosensitive resist pattern; exposing the photosensitive resist pattern in a first plasma environment formed by use of an H2-cotnaining gas so as to perform first plasma processing on the photosensitive resist pattern, in the step of the first plasma processing, a first radio frequency power supply for forming first plasma being intermittently opened; and after the first plasma processing is performed, exposing the photosensitive resist pattern in a second plasma environment formed by use of an HBr-containing gas so as to perform second plasma processing, in the step of the second plasma processing, a second radio frequency power supply for forming second plasma being intermittently opened. According to the invention, at the time when the basic morphology of the photosensitive resist is maintained, the low-frequency linewidth roughness of the photosensitive resist is effectively reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming a photoresist pattern and a method for forming a gate of a transistor. Background technique [0002] Defects in the semiconductor manufacturing process are a major factor affecting the yield and performance of semiconductor devices. Especially for today's semiconductor manufacturing industry, when the size of the device is getting smaller and smaller, the requirements for the photolithography process are particularly strict. For example, in the photolithography process, the Line Width Roughness (LWR for short) is an important indicator that is more concerned. The greater the line width roughness of the photoresist pattern, the less accurate the pattern can be transferred to the substrate, which affects the performance of the semiconductor device. [0003] For example, the existing method for forming a transistor gate includes: forming a gate material...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/027H01L21/28G03F7/00
CPCG03F7/26H01L21/0273H01L21/28
Inventor 张海洋孟晓莹
Owner SEMICON MFG INT (SHANGHAI) CORP
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