High-speed ADC (Analog to Digital Converter) sampled data receiving and buffering method and system based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides a high-speed ADC (Analog to Digital Converter) sampled data receiving and buffering method and system based on an FPGA (Field Programmable Gate Array). The system mainly comprises a data receiving delay unit, a data speed-down unit, a clock receiving delay unit, a clock processing unit, a data combination storage unit and a control unit. Inside the FPGA, the data speed-down unit is used for lowering the speed of a data signal, a clock signal uses double-edge latch data, and the data delay unit is used for performing delay adjustment on a plurality of pairs of data signals, so that simultaneous hop of the pairs of data signals is ensured; the hop edge of the clock signal is positioned in the center of the data signal; the data combination unit is used for combining and arranging widened and slowed-down data to recover practical waveform data; the practical waveform data is stored in the data storage unit. By adopting the method and the system, a plurality of paths of data signals and clock signals accompanying the data can be received simultaneously, and the functions of circular storage, pre-trigger recording, sequential read-out and the like of the data signal are realized.

Description

technical field [0001] The invention relates to a high-speed sampling data receiving and buffering method and system, based on a field programmable gate array FPGA platform and a high-speed ADC sampling data receiving and buffering method and system developed by using VHDL hardware description language. The invention relates to the field of high-speed data collection and storage. The method and system can be widely used in high-speed data collection and recording, high-speed image collection, radar echo data collection, etc., to realize real-time loop storage and pre-trigger recording of multi-channel high-speed data signals And sequential readout, after expansion, it can realize functions such as real-time analysis of high-speed data. Background technique [0002] As the application fields of the data acquisition system become more and more extensive, the requirements for its technical indicators are also getting higher and higher. Many applications require it to have a hig...

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Problems solved by technology

[0003] Most of the existing high-speed data storage methods are based on bidirectional FIFO or external storage media. The high-speed data storage based on bidirectional FIFO has the following problems. It cannot realize the pre-trigger recording of data, and can only read and write the stored data sequentially, which is prone to metastability state, etc., and the use of external storage media such as SATA hard disk, the storage speed of the sampled data is not high, it can only record the sampled data for a short time, such as the invention patent application number 200810159783.2 "FPGA-based asynchronous double FIFO Method", the invention patent with application number 200910079799.7 "Bidirectional high-speed FIFO memory based on FPGA" all use bidirectional FIFO as the storage medium, and the invention patent with application number 201010134925.7 "FPGA-based high-speed storage and transmission device" uses SATA Hard disk as storage medium, short recording time

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