Method for forming nmos metal gate transistors

A metal gate and transistor technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as poor performance of TDDB, achieve the effect of reducing the number of dangling bonds, improving the surface state, and improving the performance of TDDB

Active Publication Date: 2018-03-30
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The problem to be solved by the present invention is: the existing method for forming NMOS metal gate transistors will lead to poor TDDB performance of NMOS metal gate transistors

Method used

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  • Method for forming nmos metal gate transistors
  • Method for forming nmos metal gate transistors
  • Method for forming nmos metal gate transistors

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0047] First, if Figure 4 As shown, a substrate 100 is provided.

[0048]The substrate 100 may be a common substrate such as a silicon substrate, a silicon germanium substrate, gallium arsenic, and the like. In a specific embodiment, the substrate 100 has a P well 101 for forming an NMOS metal gate transistor at a position corresponding to the P well 101; in addition, the substrate 100 also has a shallow trench isolation structure 102 for forming the NMOS Metal gate transistors are electrically isolated from other devices on the same substrate.

[0049] Continue to refer to Figure 4 As shown, a dummy gate structure is formed on a substrate 100, and the dummy gate structure includes: a gate dielectric layer 110, a nitrogen-containing diffusion barrier layer 120 located on the gate dielectric layer 110, and a dummy gate located on the nitrogen-containing diffusion barrier layer 120 Pole 130.

[0050] The gate dielectric layer 110 may be a high-k dielectric layer, or a stac...

no. 2 example

[0088] The difference between the second embodiment and the first embodiment is: after removing the dummy gate and before performing plasma treatment, only plasma etching is performed on the bottom of the trench with fluorine-containing plasma. In other words, in the second embodiment, only one plasma etch step is utilized to remove the polymer on the surface of the nitrogen-containing diffusion barrier layer.

[0089] In this embodiment, the fluorine-containing gas is plasmatized to generate the fluorine-containing plasma, and the fluorine-containing gas includes at least CF 4 、NF 3 , SF 6 One of.

[0090] Compared with the second embodiment in which only one plasma etching step is used to remove the polymer, since the first embodiment uses two plasma etching steps to remove the polymer, each plasma in the first embodiment The ion bombardment energy in the etching step can be smaller, which reduces the damage to the nitrogen-containing diffusion barrier layer, which is con...

no. 3 example

[0093] The difference between the third embodiment and the first embodiment is that in the step of removing the dummy gate, there is no metal hard mask layer between the silicon oxide layer and the photoresist layer.

[0094] In other words, in the third embodiment, the method for removing the dummy gate includes: forming a silicon oxide layer on the interlayer dielectric layer and the dummy gate, and a photoresist layer on the silicon oxide layer; The silicon oxide layer is patterned to form an opening in the photoresist layer and the silicon oxide layer, the opening corresponds to the position of the dummy gate, and the bottom of the opening exposes the dummy gate; the patterned photoresist layer and The patterned silicon oxide layer is used as a mask for dry etching to remove the dummy gate and form a trench at the position of the dummy gate; after removing the dummy gate, the photoresist layer is removed.

[0095] In the third embodiment, the function of disposing the sili...

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Abstract

The invention discloses a forming method of an NMOS (N-channel Metal Oxide Semiconductor) metal gate transistor. The forming method comprises the following steps of providing a substrate; forming a pseudo-gate structure on the substrate, wherein the pseudo-gate structure comprises a gate dielectric layer, a nitrogen-contained diffusion barrier layer positioned on the gate dielectric layer, and a pseudo-gate positioned on the nitrogen-contained diffusion barrier layer; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer is flush with the upper surface of the pseudo-gate; removing the pseudo-gate to form a groove of which the bottom is exposed from the nitrogen-contained diffusion barrier layer, wherein after the pseudo-gate is removed, the nitrogen-contained diffusion barrier layer is exposed in an N-contained plasma environment and is subjected to plasma treatment; after the plasma treatment, forming a metal gate in the groove. By virtue of the step of plasma treatment, the TDDB (Time Dependent Dielectric Breakdown) performance of the NMOS metal gate transistor can be improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductors, in particular to a method for forming an NMOS metal gate transistor. Background technique [0002] An existing method for forming an NMOS metal gate transistor using a gate last process includes: figure 1 As shown, a substrate 1 is provided, and a shallow trench isolation structure (STI) 2 is provided in the substrate 1, which is used to electrically isolate the NMOS metal gate transistor from other devices located on the same substrate; a gate is formed on the substrate 1 Dielectric layer 3, TiN layer 4 on gate dielectric layer 3, dummy gate 5 on TiN layer 4; spacer 6 is formed around gate dielectric layer 3, TiN layer 4 and dummy gate 5; Layer 3, TiN layer 4, dummy gate 5 and spacer 6 are masks for ion implantation to form source 7a and drain 7b; an interlayer dielectric layer 8 is formed on the substrate 1, interlayer dielectric layer 8 and dummy The upper surface of grid 5 is flush; ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/336
CPCH01L29/42364H01L29/66477
Inventor 张海洋李凤莲
Owner SEMICON MFG INT (SHANGHAI) CORP
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