Semiconductor structure and forming method thereof

Abstract

A semiconductor structure and a forming method thereof are provided; the semiconductor structure comprises the following elements: a semiconductor substrate; an interlayer dielectric layer positioned on the semiconductor substrate; a metal layer positioned in the interlayer dielectric layer; a bonding layer positioned on the metal layer; a stop layer positioned on the interlayer dielectric layer and the bonding layer. A surface of the bonding layer contacting with the metal layer contains conductive material, and a surface of the bonding layer contacting with the stop layer contains insulation material. The method improves bonding property between the metal layer and the stop layer in the semiconductor structure, so the metal layer and the stop layer cannot be disengaged, thereby further improving yield and the electric performance of the semiconductor structure.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits (ULSI), the internal circuit density is increasing, and the number of components contained is increasing, so that the surface of the wafer cannot provide enough area to make the required interconnection lines (Interconnect). In order to meet the increased demand for interconnection lines after the shrinkage of components, the design of multilayer metal interconnection lines with more than two layers realized by using through holes has become a method that must be adopted in VLSI technology. [0003] Due to the low resistivity of copper metal and long electromigration life, using copper technology to make metal interconnection lines can reduce the RC (Resistive Capacitive delay) de...

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Problems solved by technology

[0004] However, when conducting the wiring bonding test (Wiring bonding test) on the above-mentioned copper interconnection structure, it was found that the barrier layer 106 in the copper interconnection structure is easily peeled off from the interlayer dielectric layer 102 and the copper interconnection line 104, resulting in delamination. ) phenomenon, resulting in low yield of the formed copper interconnect structure, and prone to electromigration failure, poor electrical performance

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