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Packaging method

A packaging method and a plastic sealing layer technology, which are applied in the manufacture of electrical components, electrical solid devices, semiconductor/solid devices, etc., can solve the problems of unfavorable electrical connection of semiconductor chips, high cost of lead frame process, and poor shape of lead frame, etc. Achieve the effect of reducing external pollution, good shape and good ductility

Active Publication Date: 2014-08-06
NANTONG FUJITSU MICROELECTRONICS
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  • Description
  • Claims
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Problems solved by technology

[0004] However, in the package structure, the process cost of forming the lead frame is high and the process is difficult, and the shape of the lead frame is poor, which is not conducive to the electrical connection of the semiconductor chip

Method used

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Embodiment Construction

[0035] As mentioned in the background, in the package structure, the process cost of forming the lead frame is high and the process is difficult, and the shape of the lead frame is poor, which is not conducive to the electrical connection of the semiconductor chip.

[0036] After research, it was found that due to figure 1 The lead frame shown is formed by etching the provided metal substrate, so the amount of metal material used is relatively large, which increases the process cost of the lead frame. Moreover, since it is more difficult to etch the metal substrate, the process difficulty of the lead frame is increased. In addition, the lead frame formed by etching the metal substrate has poor morphology, which has an adverse effect on the stability of the electrical connection of the semiconductor chip.

[0037] Specifically, in one embodiment, the forming process of the lead frame includes: providing a metal substrate, the metal substrate has a first surface and a second su...

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Abstract

The invention provides a packaging method. The packaging method includes the steps that a plastic packaging layer is formed, wherein the plastic packaging layer is provided with a plurality of bearing regions and cutting regions between the bearing regions, a plurality of first openings penetrating through the plastic packaging layer are formed in the bearing regions, and the plastic packaging layer is provided with a first surface and a second surface opposite to the first surface; an insulating layer is formed on the first surface of the plastic packaging layer, wherein a second opening is formed in the insulating layer, and the position, located at the periphery of the first openings in the bearing regions, of part of the surface of the plastic packaging layer is exposed through the second opening; the first opening and the second opening are fully filled with conductive material to form a pin structure; a chip structure is provided; the chip structure is arranged on the insulating layer on the surfaces of the bearing regions of the plastic packaging layer in an inverted mode; sealing material layers are formed the surface of the insulating layer, the surface of the chip structure and a first surface of a lead structure; cutting is conducted along the cutting regions of the plastic packaging layer to form a packaging structure. By means of the packaging method, technology is simplified, cost is lowered, and appearance and electric connection performance of the formed structure are improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a packaging method. Background technique [0002] With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portable, ultra-thin, multimedia and low-cost to meet the needs of the public, high-density, high-performance, high-reliability and low-cost packaging forms and their Assembly technology has been rapidly developed. Compared with expensive BGA (BallGrid Array) and other packaging forms, new packaging technologies that have developed rapidly in recent years, such as Quad Flat No-lead Package (QFN, Quad Flat No-leadPackage), due to its good thermal performance and electrical The advantages of performance, small size, low cost and high productivity have triggered a new revolution in the field of microelectronic packaging technology. [0003] figure 1 It is a schematic cross-sectional structure diagra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/56H01L21/60
CPCH01L2924/15311H01L2224/16245H01L21/56H01L23/3157H01L24/81
Inventor 石磊陶玉娟
Owner NANTONG FUJITSU MICROELECTRONICS
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