Electric potential induced attenuation prevention crystalline silicon battery and preparation method thereof
A potential-induced attenuation, crystalline silicon battery technology, applied in circuits, electrical components, semiconductor devices, etc., can solve the problems of reduced battery efficiency, high extinction coefficient of silicon nitride, and reduced photo-generated current, and achieves a simple method and good anti-PID , the effect of low cost
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[0029] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.
[0030] refer to figure 1 As shown, a crystalline silicon cell with resistance to potential-induced degradation includes an amorphous silicon layer 2 covering a silicon substrate 1, a Si-rich silicon nitride layer 3 for passivation, and a N-rich layer for antireflection. Silicon nitride layer 4. The thickness of the amorphous silicon layer 2 is 2-10 nm. The thickness of the Si-rich silicon nitride layer 3 is 10-30 nm. The thickness of the N-rich silicon nitride layer 4 is 40-70nm.
[0031] The specific implementation takes tubular PECVD as an example, the flow rate of the first layer of NH3 is set to 0, the flow rate of SiH4 is set to 1800 sccm, and the time is set to 15s to form a 2-10nm anti-PID dense amorphous silicon layer 2 on the surface of the silicon substrate 1 , the flow rate of the second layer of NH3 is set to 3.5slm, ...
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