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Chip preprocessing method of selective epitaxial growth germanium silicon

An epitaxial growth and pretreatment technology, which is applied in the direction of electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as inability to guarantee wafer cleanliness, affect device characteristics, germanium-silicon dislocation stress, etc., and achieve good characteristics and process Simple, quality-assured results

Active Publication Date: 2014-07-16
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a wafer pretreatment method for selective epitaxial growth of silicon germanium, which is used to solve the problem of hydrogen baking before the selective epitaxial growth of silicon germanium in the prior art. The cleanliness of the wafer is likely to cause dislocations and stress release in the epitaxial silicon germanium, which will affect the characteristics of the device on the epitaxial layer.

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  • Chip preprocessing method of selective epitaxial growth germanium silicon
  • Chip preprocessing method of selective epitaxial growth germanium silicon
  • Chip preprocessing method of selective epitaxial growth germanium silicon

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Embodiment Construction

[0028] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] See 2 to image 3 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during a...

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Abstract

The invention provides a chip preprocessing method of selective epitaxial growth germanium silicon. The method at least comprises the following steps that (1) chip pre-washing is carried out; (2) a chip after pre-washing is arranged into a reaction cavity, hydrogen goes in, the chip is heated to a preset temperature, the hydrogen reacts with an autoxidation layer on the surface of the chip, and accordingly the autoxidation layer is removed; (3) then, hydrogen chloride gas is sprayed to the surface of the chip, and hydrogen chloride reacts with metal impurities on the surface of the chip, so that the metal impurities are dissolved; (4) the reaction cavity is vacuumized, so that surplus hydrogen, hydrogen chloride and impurities in the first two steps after reaction are removed; and (5) chip temperature is adjusted germanium silicon epitaxial growth temperature, and hydrogen carrier gas and hydrogen chloride selective gas go into the reaction cavity. According to the chip processing method, a hydrogen chloride gas way in existing equipment is used, hydrogen chloride processing happens in the reaction cavity, processing time is short, the technology is simple, the cleanliness of the chip can be greatly improved, and the quality of a following germanium silicon epitaxial layer can be guaranteed.

Description

technical field [0001] The invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a wafer pretreatment method, in particular to a wafer pretreatment method for selective epitaxial growth of silicon germanium. Background technique [0002] According to Moore's Law: The feature size of integrated circuits will decrease by 30% every 18 months, the degree of integration will double, and the cost performance of products will double. In advanced CMOS, the traditional method of reducing the thickness of the gate oxide layer can no longer meet the needs of the device. Instead, use high dielectric constant materials to reduce the electrical thickness of the product, use stress technology to enhance the mobility of carriers, use ultra-low temperature ion implantation technology and laser annealing technology to achieve ultra-shallow junctions, etc. A series of new techniques and new materials are used. Among them, the most important method of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02
CPCH01L21/02046H01L21/02049H01L21/02096
Inventor 林静
Owner SEMICON MFG INT (SHANGHAI) CORP
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