Tunneling field effect transistor of vertical structure and preparation method thereof

Abstract

The invention provides a tunneling field effect transistor of a vertical structure and a preparation method thereof. The preparation method at least comprises the steps of providing an SGOI substrate which comprises an oxygen buried layer and P-type heavy dopping SiGe; sequentially sedimenting to form a silicon layer and N-type heavy dopping SiGe on the P-type heavy dopping SiGe; utilizing the photoetching and etching technology to etch the N-type heavy dopping SiGe so as to form a drain electrode on one side surface of the silicon layer; etching the silicon layer to form a ditch of a nanometer line structure or a nanometer bar structure; utilizing the chemical erosion technology to remove a part of P-type heavy dopping SiGe under the ditch so as to enable the ditch to be hung in the air, defining the P-type heave dopping SiGe on the other side opposite to the drain electrode to be a source electrode. The drain electrode, the ditch and the source electrode form a vertical structure. According to the tunneling field effect transistor of the vertical structure, the drain electrode, the ditch and the source electrode form the vertical structure, so that a tunneling area can be increased, and drive currents of elements can be improved. Further, the formed ditch hung in the air can further restrict leaked currents of elements.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a tunneling field effect transistor with a vertical structure and a preparation method thereof. Background technique [0002] In recent years, microelectronics technology with silicon integrated circuits as the core has developed rapidly. The development of integrated circuit chips basically follows Moore's law, that is, the integration level of semiconductor chips doubles every 18 months. Over the past period of time, the advancement of microelectronics technology has been based on the continuous optimization of the cost-effectiveness of materials, processes and processes. However, scaling down conventional silicon-based CMOS transistors has become increasingly difficult with the development of microelectronics technology. Moreover, most electronic products manufactured using MOSFETs today have the following main problems: First, due to the shortening of the MOSFE...

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Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a tunneling field-effect transistor with a vertical structure and its preparation method, which is used to solve the problem of small driving current and leakage of the planar tunneling field-effect transistor in the prior art. The current is still a big problem

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