pmos transistor and its forming method

Abstract

The invention provides a PMOS transistor and a forming method. The forming method of the PMOS transistor comprises the steps that a semiconductor substrate is provided, and a silicon carbide layer is formed on the surface of the semiconductor substrate; a strained silicon layer is formed on the surface of the silicon carbide layer; a grid structure is formed on the surface of the a strained silicon layer ; germanium-silicon source / drain regions are formed in positions, on two sides of the grid structure, in the silicon carbide layer. As channel regions of the PMOS transistor are located in the silicon carbide layer and the strained silicon layer, the lattice constant of the silicon carbide layer is relatively small, and compression stress is produced inside the strained silicon layer by means of the silicon carbide layer. Besides, source / drain regions are the germanium-silicon source / drain regions, and the compression stress can also be produced in the channel regions by means of the silicon carbide layer. Therefore, the migration rate of holes in the channel regions of the PMOS transistor can be improved, and electrical properties of the PMOS transistor are enhanced.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a PMOS transistor and a forming method. Background technique [0002] It is well known that stress can alter the energy gap and carrier mobility of semiconductor materials. With the in-depth research on the piezoresistance effect of semiconductor materials, the industry has gradually realized that stress can be used to increase the carrier mobility of MOS devices, that is, strained silicon technology (Strained Silicon). [0003] The U.S. patent document with publication number US2007 / 0196992A1 discloses a strained silicon CMOS transistor with silicon germanium and silicon carbide source / drain regions, please refer to figure 1 , including: a semiconductor substrate 10, the semiconductor substrate 10 includes a region A where an NMOS transistor is to be formed and a region B where a PMOS transistor is to be formed, and the adjacent region A and region B are separated by a shallow tre...

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Problems solved by technology

[0006] However, in the prior art, the silicon germanium source / drain region and the silicon carbide source / drain region of the transistor exert limited stress on the channel region under the gate structure, the improvement of carrier mobility is small, and the performance improvement of the transistor is limited. , so the industry needs MOS devices that can generate greater stress

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