TSV hole bottom medium layer etching method

A dielectric layer, all technologies, applied in the field of microelectronics, can solve the problems of increasing the difficulty of etching, damage to the insulating layer material of the sidewall of the TSV hole, etc.

Active Publication Date: 2013-10-23
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the TSV aperture becomes smaller and smaller, the use of dry etching is limited, which increases the difficulty of etching
In addition, when dry etching is used, the material of the insulating layer on the side wall of the TSV hole will also be damaged to varying degrees.

Method used

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  • TSV hole bottom medium layer etching method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0026] (1) Thinning the backside of an 8-inch, 725um-thick wafer 1 with IC devices;

[0027] A: There is a metal pad 3 inside the IC device wafer, and there is an oxide insulating layer 2 with a thickness of 1.5um between the metal pad and the IC device;

[0028] B: Use a wafer thinning machine to thin the back side of the IC device wafer 1, so that the wafer is thinned to 100um;

[0029] (2) Fabricate TSV holes 4 at the positions corresponding to the metal pads on the back of the IC device wafer 1; from the back of the wafer, fabricate TSV holes 4 by deep reactive ion etching at the position facing the metal pads 3, The aperture is 24um, when etching the TSV hole, until the oxide insulating layer 2 above the metal pad is fully exposed;

[0030] (3) Make a polymer insulating layer 5 in the TSV hole 4; make a 2um polymer insulating layer 5 on the side wall and bottom of the TSV hole by spin coating or spraying, and the polymer material is PI;

[0031] (4) Remove the polymer i...

Embodiment 2

[0035] (1) Thinning the backside of an 8-inch, 725um-thick wafer 1 with IC devices;

[0036] A: There is a metal pad 3 inside the IC device wafer, and there is an oxide insulating layer 2 with a thickness of 1.5um between the metal pad and the IC device;

[0037] B: Use a wafer thinning machine to thin the back side of the IC device wafer 1, so that the wafer is thinned to 120um;

[0038] (2) Fabricate TSV holes 4 at the positions corresponding to the metal pads on the back of the IC device wafer 1; from the back of the wafer, fabricate TSV holes 4 by deep reactive ion etching at the position facing the metal pads 3, The aperture is 36um, when etching the TSV hole 4, until the oxide insulating layer 2 above the metal pad is fully exposed;

[0039] (3) Make a polymer insulating layer 2 in the TSV hole; make a 3.5um polymer insulating layer 5 on the side wall and bottom of the TSV hole by spin coating or spraying, and the polymer material is PI;

[0040] (4) Remove the polymer...

Embodiment 3

[0044] (1) Thinning the backside of an 8-inch, 725um-thick wafer 1 with IC devices;

[0045] A: There is a metal pad 3 inside the IC device wafer, and there is an oxide insulating layer 2 with a thickness of 2um between the metal pad and the IC device;

[0046] B: Use a wafer thinning machine to thin the back of IC device wafer 1, so that the wafer is thinned to 150um;

[0047] (2) Make TSV holes 4 at the positions corresponding to the metal pads 3 on the back of the IC device wafer 1; from the back of the wafer, make TSV holes 4 at the positions facing the metal pads 3 by deep reactive ion etching , the aperture is 50um, when etching the TSV hole 4, until the oxide insulating layer 2 above the metal pad 3 is fully exposed;

[0048] (3) Make a polymer insulating layer 5 in the TSV hole 4; make a 5um polymer insulating layer 5 on the side wall and bottom of the TSV hole by spin coating or spraying, and the polymer material is PBO;

[0049] (4) Remove the polymer insulating laye...

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Abstract

The invention provides a TSV hole bottom medium layer etching method. For TSV holes with small hole diameters, the TSV hole bottom medium layer etching method can reduce TSV hole bottom medium layer etching difficulty and avoid damage to TSV side wall insulating layer materials in the etching process. The TSV hole bottom medium layer etching method includes the steps of step 1, carrying out back face thinning on a wafer comprising an IC device, step 2, manufacturing a TSV hole in a position, corresponding to a metal bonding pad, of the back face of the wafer comprising the IC device, step 3, manufacturing a polymer insulating layer in the TSV hole, step 4, removing the polymer insulating layer at the bottom of the TSV hole and enabling an oxide insulating layer at the bottom of the TSV hole to be exposed, step 5, etching the oxide insulating layer exposed out of the bottom of the TSV hole through wet processing and enabling the metal bonding pad to be exposed, and step 6, manufacturing an RDL through metal connection wires, enabling the RDL and the metal bonding pad at the bottom of the TSV to be connected, and further manufacturing a surface metal bonding pad and slight solder bumps to enable the surface metal bonding pad and the slight solder bumps to be connected with the RDL.

Description

technical field [0001] The invention relates to a method for manufacturing or processing a semiconductor or solid device in the technical field of microelectronics, in particular to a method for etching a dielectric layer at the bottom of a TSV hole. Background technique [0002] With the continuous advancement of microelectronics technology, the feature size of integrated circuits has been continuously reduced and the interconnection density has been continuously increased. At the same time, users' requirements for high performance and low power consumption continue to increase. In this case, the way to improve the performance by further reducing the line width of the interconnection is limited by the physical characteristics of the material and the equipment process, and the resistance-capacitance (RC) delay of the two-dimensional interconnection gradually becomes the limit to improve the performance of the semiconductor chip. bottleneck. The Through Silicon Via (TSV) pr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/311H01L21/768
Inventor 戴风伟于大全
Owner NAT CENT FOR ADVANCED PACKAGING
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