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Correction method and corrector for time-interleaved adc sampling time mismatch

A technology of sampling time and time interleaving, applied in the field of microelectronics, can solve problems affecting the dynamic performance of analog-to-digital converters, and achieve the effects of guaranteed performance, improved performance, and low complexity

Active Publication Date: 2016-08-10
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in reality, there are non-ideal factors such as sampling time mismatch (Timing mismatch), gain mismatch (Gain mismatch), offset mismatch (Offset mismatch) and bandwidth mismatch (Bandwidth mismatch) among the sub-ADCs of each channel. , which seriously affects the dynamic performance of the entire ADC

Method used

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  • Correction method and corrector for time-interleaved adc sampling time mismatch
  • Correction method and corrector for time-interleaved adc sampling time mismatch
  • Correction method and corrector for time-interleaved adc sampling time mismatch

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Embodiment

[0050] Taking the four-channel time-interleaved ADC as an example, such as Figure 4 As shown, its working principle is: the four clocks generated by the DLL are respectively sent to the sample and hold modules of the four channels, and the working time of the sample and hold modules of each channel is staggered. The channel ADC converts the output of the sample and hold module into a frequency fs / 8, N-bit digital codeword (wherein, f s interleaves the sampling frequency of the ADC for the entire time). The output of the channel ADC is sent to the multiplexer, and the multiplexer converts the output of each channel ADC into a frequency f s / 2 N-bit digital output.

[0051] When there is no sample time mismatch between channels, such as Figure 5 Shown by the solid line in the middle vertical line.

[0052] make:

[0053] E 1 [ k ...

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PUM

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Abstract

The present invention relates to microelectronic technology, in particular to a time-interleaved analog-to-digital converter (ADC), in particular to a correction method and a corrector for time-interleaved ADC sampling time mismatch. The method of the present invention: mainly by making a difference to the digital output of the adjacent channels of the time-interleaved ADC, to obtain the difference Ei[k], and to represent the actual sampling time between adjacent channels with the mean value Ai after its absolute value summation Gap, which represents the standard sampling time gap between adjacent channels. By obtaining the sampling time mismatch of each channel, the relative error Bi is finally eliminated by AAR filtering to eliminate statistical errors. After summing, it is fed back to the clock generation unit to adjust the channel sampling clock, so as to realize Negative Feedback Regulation of Sampling Time Mismatch. The beneficial effect of the invention is that it can effectively improve and guarantee the performance of the multi-channel time-interleaving analog-to-digital converter, and has the advantages of low complexity, small hardware overhead and easy implementation. The invention is especially suitable for high-speed low-power consumption analog-to-digital conversion.

Description

technical field [0001] The present invention relates to microelectronic technology, in particular to a time-interleaved analog-to-digital converter (ADC), in particular to a correction method and a corrector for time-interleaved ADC sampling time mismatch. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology, high-speed, highly integrated digital circuits have been developed by leaps and bounds, and the digital signal processing capability has been continuously enhanced. In order to meet the demands of high-speed digital circuits, how to increase the speed of analog-to-digital converters has become the focus of attention of integrated circuit designers. [0003] An analog-to-digital conversion system that connects multiple analog-to-digital converters in parallel and uses interleaved clocks to make them work in turn has attracted widespread attention. Its characteristic is that the overall speed is improved while maint...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03M1/10
Inventor 宁宁李靖李天柱胡勇王成碧眭志凌刘皓于奇
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA
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